mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-01-22 03:11:09 +00:00
tcg: Add gvec expanders for vector shift by scalar
Allow expansion either via shift by scalar or by replicating the scalar for shift by vector. Backports commit b4578cd91cda4cef1c413304353ca6dc5b957b60 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
0217ee7b24
commit
79b9dc559e
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@ -2906,14 +2906,17 @@
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#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64
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#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_aarch64
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64
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#define tcg_gen_gvec_sars tcg_gen_gvec_sars_aarch64
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#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_aarch64
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#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_aarch64
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#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_aarch64
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#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_aarch64
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#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_aarch64
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64
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#define tcg_gen_gvec_shls tcg_gen_gvec_shls_aarch64
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#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_aarch64
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64
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#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_aarch64
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#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_aarch64
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#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_aarch64
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#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_aarch64
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@ -3030,6 +3033,7 @@
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#define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64
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#define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64
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#define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64
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#define tcg_gen_sars_vec tcg_gen_sars_vec_aarch64
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#define tcg_gen_sarv_vec tcg_gen_sarv_vec_aarch64
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#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64
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#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64
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@ -3043,12 +3047,14 @@
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#define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64
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#define tcg_gen_shli_i64 tcg_gen_shli_i64_aarch64
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#define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64
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#define tcg_gen_shls_vec tcg_gen_shls_vec_aarch64
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#define tcg_gen_shlv_vec tcg_gen_shlv_vec_aarch64
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#define tcg_gen_shr_i32 tcg_gen_shr_i32_aarch64
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64
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#define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64
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#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64
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#define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64
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#define tcg_gen_shrs_vec tcg_gen_shrs_vec_aarch64
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#define tcg_gen_shrv_vec tcg_gen_shrv_vec_aarch64
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#define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64
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#define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64
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@ -2906,14 +2906,17 @@
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#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64eb
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#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_aarch64eb
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64eb
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#define tcg_gen_gvec_sars tcg_gen_gvec_sars_aarch64eb
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#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_aarch64eb
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#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_aarch64eb
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#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_aarch64eb
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#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_aarch64eb
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#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_aarch64eb
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64eb
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#define tcg_gen_gvec_shls tcg_gen_gvec_shls_aarch64eb
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#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_aarch64eb
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64eb
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#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_aarch64eb
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#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_aarch64eb
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#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_aarch64eb
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#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_aarch64eb
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@ -3030,6 +3033,7 @@
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#define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64eb
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#define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64eb
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#define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64eb
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#define tcg_gen_sars_vec tcg_gen_sars_vec_aarch64eb
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#define tcg_gen_sarv_vec tcg_gen_sarv_vec_aarch64eb
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#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64eb
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#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64eb
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@ -3043,12 +3047,14 @@
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#define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64eb
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#define tcg_gen_shli_i64 tcg_gen_shli_i64_aarch64eb
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#define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64eb
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#define tcg_gen_shls_vec tcg_gen_shls_vec_aarch64eb
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#define tcg_gen_shlv_vec tcg_gen_shlv_vec_aarch64eb
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#define tcg_gen_shr_i32 tcg_gen_shr_i32_aarch64eb
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64eb
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#define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64eb
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#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb
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#define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64eb
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#define tcg_gen_shrs_vec tcg_gen_shrs_vec_aarch64eb
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#define tcg_gen_shrv_vec tcg_gen_shrv_vec_aarch64eb
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#define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64eb
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#define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64eb
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@ -2906,14 +2906,17 @@
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#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_arm
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#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_arm
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_arm
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#define tcg_gen_gvec_sars tcg_gen_gvec_sars_arm
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#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_arm
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#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_arm
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#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_arm
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#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_arm
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#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_arm
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_arm
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#define tcg_gen_gvec_shls tcg_gen_gvec_shls_arm
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#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_arm
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_arm
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#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_arm
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#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_arm
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#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_arm
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#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_arm
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@ -3030,6 +3033,7 @@
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#define tcg_gen_sari_i32 tcg_gen_sari_i32_arm
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#define tcg_gen_sari_i64 tcg_gen_sari_i64_arm
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#define tcg_gen_sari_vec tcg_gen_sari_vec_arm
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#define tcg_gen_sars_vec tcg_gen_sars_vec_arm
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#define tcg_gen_sarv_vec tcg_gen_sarv_vec_arm
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#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_arm
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#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_arm
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@ -3043,12 +3047,14 @@
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#define tcg_gen_shli_i32 tcg_gen_shli_i32_arm
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#define tcg_gen_shli_i64 tcg_gen_shli_i64_arm
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#define tcg_gen_shli_vec tcg_gen_shli_vec_arm
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#define tcg_gen_shls_vec tcg_gen_shls_vec_arm
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#define tcg_gen_shlv_vec tcg_gen_shlv_vec_arm
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#define tcg_gen_shr_i32 tcg_gen_shr_i32_arm
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_arm
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#define tcg_gen_shri_i32 tcg_gen_shri_i32_arm
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#define tcg_gen_shri_i64 tcg_gen_shri_i64_arm
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#define tcg_gen_shri_vec tcg_gen_shri_vec_arm
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#define tcg_gen_shrs_vec tcg_gen_shrs_vec_arm
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#define tcg_gen_shrv_vec tcg_gen_shrv_vec_arm
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#define tcg_gen_smax_i32 tcg_gen_smax_i32_arm
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#define tcg_gen_smax_i64 tcg_gen_smax_i64_arm
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@ -2906,14 +2906,17 @@
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#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_armeb
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#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_armeb
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_armeb
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#define tcg_gen_gvec_sars tcg_gen_gvec_sars_armeb
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#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_armeb
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#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_armeb
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#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_armeb
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#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_armeb
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#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_armeb
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_armeb
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#define tcg_gen_gvec_shls tcg_gen_gvec_shls_armeb
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#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_armeb
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_armeb
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#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_armeb
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#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_armeb
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#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_armeb
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#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_armeb
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@ -3030,6 +3033,7 @@
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#define tcg_gen_sari_i32 tcg_gen_sari_i32_armeb
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#define tcg_gen_sari_i64 tcg_gen_sari_i64_armeb
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#define tcg_gen_sari_vec tcg_gen_sari_vec_armeb
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#define tcg_gen_sars_vec tcg_gen_sars_vec_armeb
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#define tcg_gen_sarv_vec tcg_gen_sarv_vec_armeb
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#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_armeb
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#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_armeb
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@ -3043,12 +3047,14 @@
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#define tcg_gen_shli_i32 tcg_gen_shli_i32_armeb
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#define tcg_gen_shli_i64 tcg_gen_shli_i64_armeb
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#define tcg_gen_shli_vec tcg_gen_shli_vec_armeb
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#define tcg_gen_shls_vec tcg_gen_shls_vec_armeb
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#define tcg_gen_shlv_vec tcg_gen_shlv_vec_armeb
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#define tcg_gen_shr_i32 tcg_gen_shr_i32_armeb
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_armeb
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#define tcg_gen_shri_i32 tcg_gen_shri_i32_armeb
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#define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb
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#define tcg_gen_shri_vec tcg_gen_shri_vec_armeb
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#define tcg_gen_shrs_vec tcg_gen_shrs_vec_armeb
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#define tcg_gen_shrv_vec tcg_gen_shrv_vec_armeb
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#define tcg_gen_smax_i32 tcg_gen_smax_i32_armeb
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#define tcg_gen_smax_i64 tcg_gen_smax_i64_armeb
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@ -2912,14 +2912,17 @@ symbols = (
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'tcg_gen_gvec_sar32v',
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'tcg_gen_gvec_sar64v',
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'tcg_gen_gvec_sari',
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'tcg_gen_gvec_sars',
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'tcg_gen_gvec_sarv',
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'tcg_gen_gvec_shl8v',
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'tcg_gen_gvec_shl16v',
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'tcg_gen_gvec_shl32v',
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'tcg_gen_gvec_shl64v',
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'tcg_gen_gvec_shli',
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'tcg_gen_gvec_shls',
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'tcg_gen_gvec_shlv',
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'tcg_gen_gvec_shri',
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'tcg_gen_gvec_shrs',
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'tcg_gen_gvec_shrv',
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'tcg_gen_gvec_shr8v',
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'tcg_gen_gvec_shr16v',
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@ -3036,6 +3039,7 @@ symbols = (
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'tcg_gen_sari_i32',
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'tcg_gen_sari_i64',
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'tcg_gen_sari_vec',
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'tcg_gen_sars_vec',
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'tcg_gen_sarv_vec',
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'tcg_gen_setcond_i32',
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'tcg_gen_setcond_i64',
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@ -3049,12 +3053,14 @@ symbols = (
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'tcg_gen_shli_i32',
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'tcg_gen_shli_i64',
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'tcg_gen_shli_vec',
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'tcg_gen_shls_vec',
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'tcg_gen_shlv_vec',
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'tcg_gen_shr_i32',
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'tcg_gen_shr_i64',
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'tcg_gen_shri_i32',
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'tcg_gen_shri_i64',
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'tcg_gen_shri_vec',
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'tcg_gen_shrs_vec',
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'tcg_gen_shrv_vec',
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'tcg_gen_smax_i32',
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'tcg_gen_smax_i64',
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#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_m68k
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#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_m68k
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_m68k
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#define tcg_gen_gvec_sars tcg_gen_gvec_sars_m68k
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#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_m68k
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#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_m68k
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#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_m68k
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#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_m68k
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#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_m68k
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_m68k
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#define tcg_gen_gvec_shls tcg_gen_gvec_shls_m68k
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#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_m68k
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_m68k
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#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_m68k
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#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_m68k
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#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_m68k
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#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_m68k
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#define tcg_gen_sari_i32 tcg_gen_sari_i32_m68k
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#define tcg_gen_sari_i64 tcg_gen_sari_i64_m68k
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#define tcg_gen_sari_vec tcg_gen_sari_vec_m68k
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#define tcg_gen_sars_vec tcg_gen_sars_vec_m68k
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#define tcg_gen_sarv_vec tcg_gen_sarv_vec_m68k
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#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_m68k
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#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_m68k
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#define tcg_gen_shli_i32 tcg_gen_shli_i32_m68k
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#define tcg_gen_shli_i64 tcg_gen_shli_i64_m68k
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#define tcg_gen_shli_vec tcg_gen_shli_vec_m68k
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#define tcg_gen_shls_vec tcg_gen_shls_vec_m68k
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#define tcg_gen_shlv_vec tcg_gen_shlv_vec_m68k
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#define tcg_gen_shr_i32 tcg_gen_shr_i32_m68k
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_m68k
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#define tcg_gen_shri_i32 tcg_gen_shri_i32_m68k
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#define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k
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#define tcg_gen_shri_vec tcg_gen_shri_vec_m68k
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#define tcg_gen_shrs_vec tcg_gen_shrs_vec_m68k
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#define tcg_gen_shrv_vec tcg_gen_shrv_vec_m68k
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#define tcg_gen_smax_i32 tcg_gen_smax_i32_m68k
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#define tcg_gen_smax_i64 tcg_gen_smax_i64_m68k
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#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_mips
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_mips
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_mips
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_mips
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_mips
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_mips
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_mips
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_mips
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_mips
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_mips
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_mips
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips64
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_mips64
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips64
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips64
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips64
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips64
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_mips64
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_mips64
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips64
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips64
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips64
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_mips64
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_mips64
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips64
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_mips64
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_mips64
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_mips64
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips64
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_mips64
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_mips64
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips64
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_mips64
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips64
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64el
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips64el
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64el
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_mips64el
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips64el
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips64el
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips64el
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips64el
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips64el
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64el
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_mips64el
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips64el
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64el
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_mips64el
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips64el
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips64el
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips64el
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64el
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64el
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_mips64el
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_mips64el
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips64el
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64el
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64el
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64el
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_mips64el
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_mips64el
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_mips64el
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips64el
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_mips64el
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_mips64el
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64el
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips64el
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_mips64el
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips64el
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64el
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64el
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mipsel
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mipsel
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mipsel
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_mipsel
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mipsel
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mipsel
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mipsel
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mipsel
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mipsel
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mipsel
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_mipsel
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mipsel
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mipsel
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_mipsel
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mipsel
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mipsel
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mipsel
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mipsel
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mipsel
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_mipsel
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_mipsel
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_mipsel
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mipsel
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mipsel
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mipsel
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_mipsel
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_mipsel
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_mipsel
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_mipsel
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_mipsel
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_mipsel
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mipsel
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mipsel
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_mipsel
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_mipsel
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mipsel
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mipsel
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_powerpc
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_powerpc
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_powerpc
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_powerpc
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_powerpc
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_powerpc
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_powerpc
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_powerpc
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_powerpc
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_powerpc
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_powerpc
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_powerpc
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_powerpc
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_powerpc
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_powerpc
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_powerpc
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_powerpc
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_powerpc
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_powerpc
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_powerpc
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_powerpc
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_powerpc
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_powerpc
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_powerpc
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_powerpc
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_powerpc
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_powerpc
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_powerpc
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_powerpc
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_powerpc
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_powerpc
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_powerpc
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_powerpc
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_powerpc
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_powerpc
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_powerpc
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_powerpc
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv32
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_riscv32
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv32
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_riscv32
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_riscv32
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_riscv32
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_riscv32
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_riscv32
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_riscv32
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv32
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_riscv32
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_riscv32
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv32
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_riscv32
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_riscv32
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_riscv32
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_riscv32
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv32
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv32
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_riscv32
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_riscv32
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_riscv32
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv32
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv32
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv32
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv32
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_riscv32
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_riscv32
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_riscv32
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_riscv32
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv32
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv32
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv32
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_riscv32
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_riscv32
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_riscv32
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv32
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv32
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv64
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_riscv64
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv64
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_riscv64
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_riscv64
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_riscv64
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_riscv64
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_riscv64
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_riscv64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv64
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_riscv64
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_riscv64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv64
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_riscv64
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_riscv64
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_riscv64
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_riscv64
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv64
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv64
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_riscv64
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_riscv64
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_riscv64
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv64
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv64
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv64
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv64
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_riscv64
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_riscv64
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_riscv64
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_riscv64
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv64
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv64
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv64
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_riscv64
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_riscv64
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_riscv64
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv64
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv64
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_sparc
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_sparc
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_sparc
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_sparc
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_sparc
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_sparc
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_sparc
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_sparc
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_sparc
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_sparc
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_sparc
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_sparc
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_sparc
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_sparc
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_sparc
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_sparc
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_sparc
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_sparc
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_sparc
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_sparc
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_sparc
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_sparc
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_sparc
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_sparc
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_sparc
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc64
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_sparc64
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc64
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_sparc64
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_sparc64
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_sparc64
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_sparc64
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_sparc64
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_sparc64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc64
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_sparc64
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_sparc64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc64
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_sparc64
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_sparc64
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_sparc64
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_sparc64
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc64
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc64
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_sparc64
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_sparc64
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_sparc64
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc64
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc64
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc64
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_sparc64
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_sparc64
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_sparc64
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_sparc64
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_sparc64
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_sparc64
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc64
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_sparc64
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_sparc64
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_sparc64
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc64
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc64
|
||||
|
|
|
|||
|
|
@ -2557,6 +2557,220 @@ void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Specialized generation vector shifts by a non-constant scalar.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
void (*fni4)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32);
|
||||
void (*fni8)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64);
|
||||
void (*fniv_s)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_i32);
|
||||
void (*fniv_v)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
|
||||
gen_helper_gvec_2 *fno[4];
|
||||
TCGOpcode s_list[2];
|
||||
TCGOpcode v_list[2];
|
||||
} GVecGen2sh;
|
||||
|
||||
static void expand_2sh_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t oprsz, uint32_t tysz, TCGType type,
|
||||
TCGv_i32 shift,
|
||||
void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_i32))
|
||||
{
|
||||
TCGv_vec t0 = tcg_temp_new_vec(s, type);
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += tysz) {
|
||||
tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
|
||||
fni(s, vece, t0, t0, shift);
|
||||
tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i);
|
||||
}
|
||||
tcg_temp_free_vec(s, t0);
|
||||
}
|
||||
|
||||
static void
|
||||
do_gvec_shifts(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,
|
||||
uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g)
|
||||
{
|
||||
TCGType type;
|
||||
uint32_t some;
|
||||
|
||||
check_size_align(oprsz, maxsz, dofs | aofs);
|
||||
check_overlap_2(dofs, aofs, maxsz);
|
||||
|
||||
/* If the backend has a scalar expansion, great. */
|
||||
type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64);
|
||||
if (type) {
|
||||
const TCGOpcode *hold_list = tcg_swap_vecop_list(s, NULL);
|
||||
switch (type) {
|
||||
case TCG_TYPE_V256:
|
||||
some = QEMU_ALIGN_DOWN(oprsz, 32);
|
||||
expand_2sh_vec(s, vece, dofs, aofs, some, 32,
|
||||
TCG_TYPE_V256, shift, g->fniv_s);
|
||||
if (some == oprsz) {
|
||||
break;
|
||||
}
|
||||
dofs += some;
|
||||
aofs += some;
|
||||
oprsz -= some;
|
||||
maxsz -= some;
|
||||
/* fallthru */
|
||||
case TCG_TYPE_V128:
|
||||
expand_2sh_vec(s, vece, dofs, aofs, oprsz, 16,
|
||||
TCG_TYPE_V128, shift, g->fniv_s);
|
||||
break;
|
||||
case TCG_TYPE_V64:
|
||||
expand_2sh_vec(s, vece, dofs, aofs, oprsz, 8,
|
||||
TCG_TYPE_V64, shift, g->fniv_s);
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
tcg_swap_vecop_list(s, hold_list);
|
||||
goto clear_tail;
|
||||
}
|
||||
|
||||
/* If the backend supports variable vector shifts, also cool. */
|
||||
type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64);
|
||||
if (type) {
|
||||
const TCGOpcode *hold_list = tcg_swap_vecop_list(s, NULL);
|
||||
TCGv_vec v_shift = tcg_temp_new_vec(s, type);
|
||||
|
||||
if (vece == MO_64) {
|
||||
TCGv_i64 sh64 = tcg_temp_new_i64(s);
|
||||
tcg_gen_extu_i32_i64(s, sh64, shift);
|
||||
tcg_gen_dup_i64_vec(s, MO_64, v_shift, sh64);
|
||||
tcg_temp_free_i64(s, sh64);
|
||||
} else {
|
||||
tcg_gen_dup_i32_vec(s, vece, v_shift, shift);
|
||||
}
|
||||
|
||||
switch (type) {
|
||||
case TCG_TYPE_V256:
|
||||
some = QEMU_ALIGN_DOWN(oprsz, 32);
|
||||
expand_2s_vec(s, vece, dofs, aofs, some, 32, TCG_TYPE_V256,
|
||||
v_shift, false, g->fniv_v);
|
||||
if (some == oprsz) {
|
||||
break;
|
||||
}
|
||||
dofs += some;
|
||||
aofs += some;
|
||||
oprsz -= some;
|
||||
maxsz -= some;
|
||||
/* fallthru */
|
||||
case TCG_TYPE_V128:
|
||||
expand_2s_vec(s, vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
|
||||
v_shift, false, g->fniv_v);
|
||||
break;
|
||||
case TCG_TYPE_V64:
|
||||
expand_2s_vec(s, vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
|
||||
v_shift, false, g->fniv_v);
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
tcg_temp_free_vec(s, v_shift);
|
||||
tcg_swap_vecop_list(s, hold_list);
|
||||
goto clear_tail;
|
||||
}
|
||||
|
||||
/* Otherwise fall back to integral... */
|
||||
if (vece == MO_32 && check_size_impl(oprsz, 4)) {
|
||||
expand_2s_i32(s, dofs, aofs, oprsz, shift, false, g->fni4);
|
||||
} else if (vece == MO_64 && check_size_impl(oprsz, 8)) {
|
||||
TCGv_i64 sh64 = tcg_temp_new_i64(s);
|
||||
tcg_gen_extu_i32_i64(s, sh64, shift);
|
||||
expand_2s_i64(s, dofs, aofs, oprsz, sh64, false, g->fni8);
|
||||
tcg_temp_free_i64(s, sh64);
|
||||
} else {
|
||||
TCGv_ptr a0 = tcg_temp_new_ptr(s);
|
||||
TCGv_ptr a1 = tcg_temp_new_ptr(s);
|
||||
TCGv_i32 desc = tcg_temp_new_i32(s);
|
||||
|
||||
tcg_gen_shli_i32(s, desc, shift, SIMD_DATA_SHIFT);
|
||||
tcg_gen_ori_i32(s, desc, desc, simd_desc(oprsz, maxsz, 0));
|
||||
tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
|
||||
tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
|
||||
|
||||
g->fno[vece](s, a0, a1, desc);
|
||||
|
||||
tcg_temp_free_ptr(s, a0);
|
||||
tcg_temp_free_ptr(s, a1);
|
||||
tcg_temp_free_i32(s, desc);
|
||||
return;
|
||||
}
|
||||
|
||||
clear_tail:
|
||||
if (oprsz < maxsz) {
|
||||
expand_clr(s, dofs + oprsz, maxsz - oprsz);
|
||||
}
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_shls(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen2sh g = {
|
||||
.fni4 = tcg_gen_shl_i32,
|
||||
.fni8 = tcg_gen_shl_i64,
|
||||
.fniv_s = tcg_gen_shls_vec,
|
||||
.fniv_v = tcg_gen_shlv_vec,
|
||||
.fno = {
|
||||
gen_helper_gvec_shl8i,
|
||||
gen_helper_gvec_shl16i,
|
||||
gen_helper_gvec_shl32i,
|
||||
gen_helper_gvec_shl64i,
|
||||
},
|
||||
.s_list = { INDEX_op_shls_vec, 0 },
|
||||
.v_list = { INDEX_op_shlv_vec, 0 },
|
||||
};
|
||||
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
do_gvec_shifts(s, vece, dofs, aofs, shift, oprsz, maxsz, &g);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_shrs(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen2sh g = {
|
||||
.fni4 = tcg_gen_shr_i32,
|
||||
.fni8 = tcg_gen_shr_i64,
|
||||
.fniv_s = tcg_gen_shrs_vec,
|
||||
.fniv_v = tcg_gen_shrv_vec,
|
||||
.fno = {
|
||||
gen_helper_gvec_shr8i,
|
||||
gen_helper_gvec_shr16i,
|
||||
gen_helper_gvec_shr32i,
|
||||
gen_helper_gvec_shr64i,
|
||||
},
|
||||
.s_list = { INDEX_op_shrs_vec, 0 },
|
||||
.v_list = { INDEX_op_shrv_vec, 0 },
|
||||
};
|
||||
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
do_gvec_shifts(s, vece, dofs, aofs, shift, oprsz, maxsz, &g);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_sars(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen2sh g = {
|
||||
.fni4 = tcg_gen_sar_i32,
|
||||
.fni8 = tcg_gen_sar_i64,
|
||||
.fniv_s = tcg_gen_sars_vec,
|
||||
.fniv_v = tcg_gen_sarv_vec,
|
||||
.fno = {
|
||||
gen_helper_gvec_sar8i,
|
||||
gen_helper_gvec_sar16i,
|
||||
gen_helper_gvec_sar32i,
|
||||
gen_helper_gvec_sar64i,
|
||||
},
|
||||
.s_list = { INDEX_op_sars_vec, 0 },
|
||||
.v_list = { INDEX_op_sarv_vec, 0 },
|
||||
};
|
||||
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
do_gvec_shifts(s, vece, dofs, aofs, shift, oprsz, maxsz, &g);
|
||||
}
|
||||
|
||||
/*
|
||||
* Expand D = A << (B % element bits)
|
||||
*
|
||||
|
|
|
|||
|
|
@ -313,6 +313,13 @@ void tcg_gen_gvec_shri(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof
|
|||
void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
int64_t shift, uint32_t oprsz, uint32_t maxsz);
|
||||
|
||||
void tcg_gen_gvec_shls(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_shrs(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_sars(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
|
||||
|
||||
/*
|
||||
* Perform vector shift by vector element, modulo the element size.
|
||||
* E.g. D[i] = A[i] << (B[i] % (8 << vece)).
|
||||
|
|
|
|||
|
|
@ -603,3 +603,57 @@ void tcg_gen_sarv_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv
|
|||
{
|
||||
do_op3(s, vece, r, a, b, INDEX_op_sarv_vec);
|
||||
}
|
||||
|
||||
static void do_shifts(TCGContext *tcg_ctx, unsigned vece, TCGv_vec r, TCGv_vec a,
|
||||
TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v)
|
||||
{
|
||||
TCGTemp *rt = tcgv_vec_temp(tcg_ctx, r);
|
||||
TCGTemp *at = tcgv_vec_temp(tcg_ctx, a);
|
||||
TCGTemp *st = tcgv_i32_temp(tcg_ctx, s);
|
||||
TCGArg ri = temp_arg(rt);
|
||||
TCGArg ai = temp_arg(at);
|
||||
TCGArg si = temp_arg(st);
|
||||
TCGType type = rt->base_type;
|
||||
const TCGOpcode *hold_list;
|
||||
int can;
|
||||
|
||||
tcg_debug_assert(at->base_type >= type);
|
||||
tcg_assert_listed_vecop(tcg_ctx, opc_s);
|
||||
hold_list = tcg_swap_vecop_list(tcg_ctx, NULL);
|
||||
|
||||
can = tcg_can_emit_vec_op(opc_s, type, vece);
|
||||
if (can > 0) {
|
||||
vec_gen_3(tcg_ctx, opc_s, type, vece, ri, ai, si);
|
||||
} else if (can < 0) {
|
||||
tcg_expand_vec_op(tcg_ctx, opc_s, type, vece, ri, ai, si);
|
||||
} else {
|
||||
TCGv_vec vec_s = tcg_temp_new_vec(tcg_ctx, type);
|
||||
|
||||
if (vece == MO_64) {
|
||||
TCGv_i64 s64 = tcg_temp_new_i64(tcg_ctx);
|
||||
tcg_gen_extu_i32_i64(tcg_ctx, s64, s);
|
||||
tcg_gen_dup_i64_vec(tcg_ctx, MO_64, vec_s, s64);
|
||||
tcg_temp_free_i64(tcg_ctx, s64);
|
||||
} else {
|
||||
tcg_gen_dup_i32_vec(tcg_ctx, vece, vec_s, s);
|
||||
}
|
||||
do_op3(tcg_ctx, vece, r, a, vec_s, opc_v);
|
||||
tcg_temp_free_vec(tcg_ctx, vec_s);
|
||||
}
|
||||
tcg_swap_vecop_list(tcg_ctx, hold_list);
|
||||
}
|
||||
|
||||
void tcg_gen_shls_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
|
||||
{
|
||||
do_shifts(s, vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_shrs_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
|
||||
{
|
||||
do_shifts(s, vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_sars_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
|
||||
{
|
||||
do_shifts(s, vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1000,6 +1000,10 @@ void tcg_gen_shli_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64
|
|||
void tcg_gen_shri_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
void tcg_gen_sari_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
|
||||
void tcg_gen_shls_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
|
||||
void tcg_gen_shrs_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
|
||||
void tcg_gen_sars_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
|
||||
|
||||
void tcg_gen_shlv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
|
||||
void tcg_gen_shrv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
|
||||
void tcg_gen_sarv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
|
||||
|
|
|
|||
|
|
@ -2906,14 +2906,17 @@
|
|||
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_x86_64
|
||||
#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_x86_64
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_x86_64
|
||||
#define tcg_gen_gvec_sars tcg_gen_gvec_sars_x86_64
|
||||
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_x86_64
|
||||
#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_x86_64
|
||||
#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_x86_64
|
||||
#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_x86_64
|
||||
#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_x86_64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_x86_64
|
||||
#define tcg_gen_gvec_shls tcg_gen_gvec_shls_x86_64
|
||||
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_x86_64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_x86_64
|
||||
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_x86_64
|
||||
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_x86_64
|
||||
#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_x86_64
|
||||
#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_x86_64
|
||||
|
|
@ -3030,6 +3033,7 @@
|
|||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_x86_64
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_x86_64
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_x86_64
|
||||
#define tcg_gen_sars_vec tcg_gen_sars_vec_x86_64
|
||||
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_x86_64
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_x86_64
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_x86_64
|
||||
|
|
@ -3043,12 +3047,14 @@
|
|||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_x86_64
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_x86_64
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_x86_64
|
||||
#define tcg_gen_shls_vec tcg_gen_shls_vec_x86_64
|
||||
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_x86_64
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_x86_64
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_x86_64
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_x86_64
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_x86_64
|
||||
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_x86_64
|
||||
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_x86_64
|
||||
#define tcg_gen_smax_i32 tcg_gen_smax_i32_x86_64
|
||||
#define tcg_gen_smax_i64 tcg_gen_smax_i64_x86_64
|
||||
|
|
|
|||
Loading…
Reference in a new issue