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target/arm: Use gvec for NEON_3R_VADD_VSUB insns

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Backports commit e4717ae02dd0c2e544a07302c1ed473775209aba from qemu
This commit is contained in:
Richard Henderson 2018-11-10 10:08:19 -05:00 committed by Lioncash
parent 0965b9513a
commit 7b4b5ac249
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 10 additions and 19 deletions
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29
qemu/target/arm/translate.c
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@ -6113,6 +6113,16 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break; break;
} }
return 0; return 0;
case NEON_3R_VADD_VSUB:
if (u) {
tcg_gen_gvec_sub(tcg_ctx, size, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
} else {
tcg_gen_gvec_add(tcg_ctx, size, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
}
return 0;
} }
if (size == 3) { if (size == 3) {
/* 64-bit element instructions. */ /* 64-bit element instructions. */
@ -6170,13 +6180,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
s->V1, s->V0); s->V1, s->V0);
} }
break; break;
case NEON_3R_VADD_VSUB:
if (u) {
tcg_gen_sub_i64(tcg_ctx, CPU_V001);
} else {
tcg_gen_add_i64(tcg_ctx, CPU_V001);
}
break;
default: default:
abort(); abort();
} }
@ -6311,18 +6314,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp2 = neon_load_reg(s, rd, pass); tmp2 = neon_load_reg(s, rd, pass);
gen_neon_add(s, size, tmp, tmp2); gen_neon_add(s, size, tmp, tmp2);
break; break;
case NEON_3R_VADD_VSUB:
if (!u) { /* VADD */
gen_neon_add(s, size, tmp, tmp2);
} else { /* VSUB */
switch (size) {
case 0: gen_helper_neon_sub_u8(tcg_ctx, tmp, tmp, tmp2); break;
case 1: gen_helper_neon_sub_u16(tcg_ctx, tmp, tmp, tmp2); break;
case 2: tcg_gen_sub_i32(tcg_ctx, tmp, tmp, tmp2); break;
default: abort();
}
}
break;
case NEON_3R_VTST_VCEQ: case NEON_3R_VTST_VCEQ:
if (!u) { /* VTST */ if (!u) { /* VTST */
switch (size) { switch (size) {