yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-10 22:15:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns

Browse source 
The syscall and sysret instructions behave a bit differently:
TF is checked after the instruction completes.
This allows the o/s to disable #DB at a syscall by adding TF to FMASK.
And then when the sysret is executed the #DB is taken "as if" the
syscall insn just completed.

Backports commit c52ab08aee6f7d4717fc6b517174043126bd302f from qemu
This commit is contained in:
Doug Evans 2018-03-01 10:56:02 -05:00 committed by Lioncash
parent f6e624d97b
commit 7c874b1b2b
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 33 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
qemu/target-i386/bpt_helper.c
View file

@ -243,6 +243,13 @@ void helper_single_step(CPUX86State *env)
raise_exception(env, EXCP01_DB);
}
void helper_rechecking_single_step(CPUX86State *env)
{
if ((env->eflags & TF_MASK) != 0) {
helper_single_step(env);
}
}
void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
{
#ifndef CONFIG_USER_ONLY

1
qemu/target-i386/helper.h
View file

@ -81,6 +81,7 @@ DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl)
DEF_HELPER_2(cmpxchg16b, void, env, tl)
#endif
DEF_HELPER_1(single_step, void, env)
DEF_HELPER_1(rechecking_single_step, void, env)
DEF_HELPER_1(cpuid, void, env)
DEF_HELPER_1(rdtsc, void, env)
DEF_HELPER_1(rdtscp, void, env)

31
qemu/target-i386/translate.c
View file

@ -2837,8 +2837,10 @@ static void gen_bnd_jmp(DisasContext *s)
}
/* Generate an end of block. Trace exception is also generated if needed.
If IIM, set HF_INHIBIT_IRQ_MASK if it isn't already set. */
static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit)
If INHIBIT, set HF_INHIBIT_IRQ_MASK if it isn't already set.
If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of
S->TF. This is used by the syscall/sysret insns. */
static void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
@ -2856,18 +2858,28 @@ static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit)
}
if (s->singlestep_enabled) {
gen_helper_debug(tcg_ctx, tcg_ctx->cpu_env);
} else if (recheck_tf) {
gen_helper_rechecking_single_step(tcg_ctx, tcg_ctx->cpu_env);
tcg_gen_exit_tb(tcg_ctx, 0);
} else if (s->tf) {
gen_helper_single_step(tcg_ctx, tcg_ctx->cpu_env);
} else {
tcg_gen_exit_tb(s->uc->tcg_ctx, 0);
tcg_gen_exit_tb(tcg_ctx, 0);
}
s->is_jmp = DISAS_TB_JUMP;
}
/* End of block.
If INHIBIT, set HF_INHIBIT_IRQ_MASK if it isn't already set. */
static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit)
{
gen_eob_worker(s, inhibit, false);
}
/* End of block, resetting the inhibit irq flag. */
static void gen_eob(DisasContext *s)
{
gen_eob_inhibit_irq(s, false);
gen_eob_worker(s, false, false);
}
/* generate a jump to eip. No segment change must happen before as a
@ -7089,7 +7101,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_const_i32(tcg_ctx, s->pc - s->cs_base));
set_cc_op(s, CC_OP_EFLAGS);
}
gen_eob(s);
/* TF handling for the syscall insn is different. The TF bit is checked
after the syscall insn completes. This allows #DB to not be
generated after one has entered CPL0 if TF is set in FMASK. */
gen_eob_worker(s, false, true);
break;
case 0xe8: /* call im */
{
@ -7797,7 +7812,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->lma) {
set_cc_op(s, CC_OP_EFLAGS);
}
gen_eob(s);
/* TF handling for the sysret insn is different. The TF bit is
checked after the sysret insn completes. This allows #DB to be
generated "as if" the syscall insn in userspace has just
completed. */
gen_eob_worker(s, false, true);
}
break;
#endif