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target/sparc: Add TLB entry with attributes

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Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.

Backports commit 9bed46e67e2ee54bc596ba58063ee71a5ca40923 from qemu
This commit is contained in:
Tony Nguyen 2020-01-07 19:19:19 -05:00 committed by Lioncash
parent a95927de1d
commit 7eea07fe55
1 changed files with 18 additions and 14 deletions
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32
qemu/target/sparc/mmu_helper.c
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@ -86,7 +86,7 @@ static const int perm_table[2][8] = {
};
static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
int *prot, int *access_index,
int *prot, int *access_index, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
@ -233,6 +233,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
target_ulong vaddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
MemTxAttrs attrs = {};
/*
* TODO: If we ever need tlb_vaddr_to_host for this target,
@ -243,7 +244,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
assert(!probe);
address &= TARGET_PAGE_MASK;
error_code = get_physical_address(env, &paddr, &prot, &access_index,
error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
address, access_type,
mmu_idx, &page_size);
vaddr = address;
@ -523,8 +524,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
return 0;
}
static int get_physical_address_data(CPUSPARCState *env,
hwaddr *physical, int *prot,
static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
int *prot, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx)
{
CPUState *cs = env_cpu(env);
@ -642,8 +643,8 @@ static int get_physical_address_data(CPUSPARCState *env,
return 1;
}
static int get_physical_address_code(CPUSPARCState *env,
hwaddr *physical, int *prot,
static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
int *prot, MemTxAttrs *attrs,
target_ulong address, int mmu_idx)
{
CPUState *cs = env_cpu(env);
@ -720,7 +721,7 @@ static int get_physical_address_code(CPUSPARCState *env,
}
static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
int *prot, int *access_index,
int *prot, int *access_index, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
@ -750,11 +751,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
}
if (rw == 2) {
return get_physical_address_code(env, physical, prot, address,
return get_physical_address_code(env, physical, prot, attrs, address,
mmu_idx);
} else {
return get_physical_address_data(env, physical, prot, address, rw,
mmu_idx);
return get_physical_address_data(env, physical, prot, attrs, address,
rw, mmu_idx);
}
}
@ -768,10 +769,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
target_ulong vaddr;
hwaddr paddr;
target_ulong page_size;
MemTxAttrs attrs = {};
int error_code = 0, prot, access_index;
address &= TARGET_PAGE_MASK;
error_code = get_physical_address(env, &paddr, &prot, &access_index,
error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
address, access_type,
mmu_idx, &page_size);
if (likely(error_code == 0)) {
@ -781,7 +783,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
// env->dmmu.mmu_primary_context,
// env->dmmu.mmu_secondary_context);
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,
page_size);
return true;
}
if (probe) {
@ -883,9 +886,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
{
target_ulong page_size;
int prot, access_index;
MemTxAttrs attrs = {};
return get_physical_address(env, phys, &prot, &access_index, addr, rw,
mmu_idx, &page_size);
return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
rw, mmu_idx, &page_size);
}
#if defined(TARGET_SPARC64)