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target/arm: Fix Cortex-R5F MVFR values

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The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.

Backports commit 3de79d335c9aa7d726865e3933d9b21781032183 from qemu
This commit is contained in:
Peter Maydell 2019-06-13 16:36:43 -04:00 committed by Lioncash
parent b3cfede44f
commit 808d929d7c
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1 changed files with 2 additions and 0 deletions
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qemu/target/arm/cpu.c
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@ -1304,6 +1304,8 @@ static void cortex_r5f_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cortex_r5_initfn(uc, obj, opaque); cortex_r5_initfn(uc, obj, opaque);
set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP3);
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x00000011;
} }
static const ARMCPRegInfo cortexa8_cp_reginfo[] = { static const ARMCPRegInfo cortexa8_cp_reginfo[] = {