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target/mips: Define a bit for MXU in insn_flags

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Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Backports commit a031ac61619294ae473a78d1834e757fad8b59e5 from qemu
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Craig Janeczek 2018-11-11 05:52:14 -05:00 committed by Lioncash
parent 58dc377890
commit 8429d98b40
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qemu/target/mips/mips-defs.h
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@ -65,6 +65,7 @@
* bits 56-63: vendor-specific ASEs * bits 56-63: vendor-specific ASEs
*/ */
#define ASE_MMI 0x0100000000000000ULL #define ASE_MMI 0x0100000000000000ULL
#define ASE_MXU 0x0200000000000000ULL
/* MIPS CPU defines. */ /* MIPS CPU defines. */
#define CPU_MIPS1 (ISA_MIPS1) #define CPU_MIPS1 (ISA_MIPS1)