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target/mips: Add opcodes for nanoMIPS EVA instructions

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Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.

Backports commit 0d30b3bbc5fed12da8f8d1bfd28f2803d65a4cb0 from qemu
This commit is contained in:
Dimitrije Nikolic 2018-10-23 14:33:01 -04:00 committed by Lioncash
parent c3541a4b48
commit 856974c7b2
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 34 additions and 0 deletions
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34
qemu/target/mips/translate.c
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@ -17253,6 +17253,40 @@ enum {
NM_P_SC = 0x0b, NM_P_SC = 0x0b,
}; };
/* P.LS.E0 instruction pool */
enum {
NM_LBE = 0x00,
NM_SBE = 0x01,
NM_LBUE = 0x02,
NM_P_PREFE = 0x03,
NM_LHE = 0x04,
NM_SHE = 0x05,
NM_LHUE = 0x06,
NM_CACHEE = 0x07,
NM_LWE = 0x08,
NM_SWE = 0x09,
NM_P_LLE = 0x0a,
NM_P_SCE = 0x0b,
};
/* P.PREFE instruction pool */
enum {
NM_SYNCIE = 0x00,
NM_PREFE = 0x01,
};
/* P.LLE instruction pool */
enum {
NM_LLE = 0x00,
NM_LLWPE = 0x01,
};
/* P.SCE instruction pool */
enum {
NM_SCE = 0x00,
NM_SCWPE = 0x01,
};
/* P.LS.WM instruction pool */ /* P.LS.WM instruction pool */
enum { enum {
NM_LWM = 0x00, NM_LWM = 0x00,