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target/mips: Clean up handling of CP0 register 2

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Clean up handling of CP0 register 2.

Backports commit 6d27d5bd73489a0560a6613e2b5633e221999db9 from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 22:38:44 -05:00 committed by Lioncash
parent 9450b71a13
commit 8644845898
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 41 additions and 34 deletions
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7
qemu/target/mips/cpu.h
View file

@ -291,6 +291,13 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
#define CP0_REG02__TCSTATUS 1
#define CP0_REG02__TCBIND 2
#define CP0_REG02__TCRESTART 3
#define CP0_REG02__TCHALT 4
#define CP0_REG02__TCCONTEXT 5
#define CP0_REG02__TCSCHEDULE 6
#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1

68
qemu/target/mips/translate.c
View file

@ -6716,7 +6716,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_02:
switch (sel) {
case 0:
case CP0_REG02__ENTRYLO0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(ctx, arg, offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
@ -6798,7 +6798,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_02:
switch (sel) {
case 0:
case CP0_REG02__ENTRYLO0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(s, arg, arg, mask);
gen_mthc0_entrylo(ctx, arg, offsetof(CPUMIPSState, CP0_EntryLo0));
@ -6972,7 +6972,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
case 0:
case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
tcg_gen_ld_i64(tcg_ctx, tmp, tcg_ctx->cpu_env,
@ -6989,37 +6989,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "EntryLo0";
break;
case 1:
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCStatus";
break;
case 2:
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCBind";
break;
case 3:
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCRestart";
break;
case 4:
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCHalt";
break;
case 5:
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCContext";
break;
case 6:
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCSchedule";
break;
case 7:
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCScheFBack";
@ -7730,41 +7730,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
case 0:
case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "EntryLo0";
break;
case 1:
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCStatus";
break;
case 2:
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCBind";
break;
case 3:
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCRestart";
break;
case 4:
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCHalt";
break;
case 5:
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCContext";
break;
case 6:
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCSchedule";
break;
case 7:
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCScheFBack";
@ -8470,41 +8470,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
case 0:
case CP0_REG02__ENTRYLO0:
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
case 1:
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCStatus";
break;
case 2:
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCBind";
break;
case 3:
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcrestart(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCRestart";
break;
case 4:
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tchalt(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCHalt";
break;
case 5:
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tccontext(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCContext";
break;
case 6:
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschedule(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCSchedule";
break;
case 7:
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschefback(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "TCScheFBack";
@ -9181,41 +9181,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
case 0:
case CP0_REG02__ENTRYLO0:
gen_helper_dmtc0_entrylo0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "EntryLo0";
break;
case 1:
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCStatus";
break;
case 2:
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCBind";
break;
case 3:
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCRestart";
break;
case 4:
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCHalt";
break;
case 5:
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCContext";
break;
case 6:
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCSchedule";
break;
case 7:
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "TCScheFBack";