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Add missing bit for SSE instr in VEX decoding

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The 2-byte VEX prefix imples a leading 0Fh opcode byte.

Backports commit e0014d4b3a955cfd8d517674703bfa87f340290a from qemu
This commit is contained in:
Eugene Minibaev 2018-04-10 08:49:07 -04:00 committed by Lioncash
parent 4a1de154ef
commit 87180dd231
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 1 deletions
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4
qemu/target/i386/translate.c
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@ -5202,9 +5202,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#endif #endif
rex_r = (~vex2 >> 4) & 8; rex_r = (~vex2 >> 4) & 8;
if (b == 0xc5) { if (b == 0xc5) {
/* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */
vex3 = vex2; vex3 = vex2;
b = x86_ldub_code(env, s); b = x86_ldub_code(env, s) | 0x100;
} else { } else {
/* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
s->rex_x = (~vex2 >> 3) & 8; s->rex_x = (~vex2 >> 3) & 8;
s->rex_b = (~vex2 >> 2) & 8; s->rex_b = (~vex2 >> 2) & 8;