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target/arm: Update timer access for VHE
Backports commit 5bc8437136fb1e7bc8b566f4f2f7269b0f990fad from qemu
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d6150127b4
commit
8c7795dc04
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@ -2106,10 +2106,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
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* Writable only at the highest implemented exception level.
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*/
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int el = arm_current_el(env);
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uint64_t hcr;
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uint32_t cntkctl;
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switch (el) {
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case 0:
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if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
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hcr = arm_hcr_el2_eff(env);
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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cntkctl = env->cp15.cnthctl_el2;
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} else {
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cntkctl = env->cp15.c14_cntkctl;
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}
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if (!extract32(cntkctl, 0, 2)) {
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return CP_ACCESS_TRAP;
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}
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break;
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@ -2137,17 +2145,47 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
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{
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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uint64_t hcr = arm_hcr_el2_eff(env);
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/* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
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if (cur_el == 0 &&
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!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
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return CP_ACCESS_TRAP;
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}
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switch (cur_el) {
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case 0:
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/* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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return (extract32(env->cp15.cnthctl_el2, timeridx, 1)
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? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
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}
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if (arm_feature(env, ARM_FEATURE_EL2) &&
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timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
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!extract32(env->cp15.cnthctl_el2, 0, 1)) {
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return CP_ACCESS_TRAP_EL2;
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/* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
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if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
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return CP_ACCESS_TRAP;
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}
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/* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
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if (hcr & HCR_E2H) {
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if (timeridx == GTIMER_PHYS &&
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!extract32(env->cp15.cnthctl_el2, 10, 1)) {
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return CP_ACCESS_TRAP_EL2;
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}
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} else {
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/* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
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if (arm_feature(env, ARM_FEATURE_EL2) &&
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timeridx == GTIMER_PHYS && !secure &&
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!extract32(env->cp15.cnthctl_el2, 1, 1)) {
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return CP_ACCESS_TRAP_EL2;
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}
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}
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break;
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case 1:
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/* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
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if (arm_feature(env, ARM_FEATURE_EL2) &&
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timeridx == GTIMER_PHYS && !secure &&
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(hcr & HCR_E2H
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? !extract32(env->cp15.cnthctl_el2, 10, 1)
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: !extract32(env->cp15.cnthctl_el2, 0, 1))) {
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return CP_ACCESS_TRAP_EL2;
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}
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break;
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}
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return CP_ACCESS_OK;
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}
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@ -2157,19 +2195,41 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
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{
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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uint64_t hcr = arm_hcr_el2_eff(env);
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/* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
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* EL0[PV]TEN is zero.
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*/
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if (cur_el == 0 &&
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!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
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return CP_ACCESS_TRAP;
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}
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switch (cur_el) {
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case 0:
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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/* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
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return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
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? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
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}
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if (arm_feature(env, ARM_FEATURE_EL2) &&
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timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
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!extract32(env->cp15.cnthctl_el2, 1, 1)) {
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return CP_ACCESS_TRAP_EL2;
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/*
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* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
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* EL0 if EL0[PV]TEN is zero.
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*/
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if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
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return CP_ACCESS_TRAP;
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}
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/* fall through */
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case 1:
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if (arm_feature(env, ARM_FEATURE_EL2) &&
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timeridx == GTIMER_PHYS && !secure) {
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if (hcr & HCR_E2H) {
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/* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
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if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
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return CP_ACCESS_TRAP_EL2;
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}
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} else {
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/* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
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if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
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return CP_ACCESS_TRAP_EL2;
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}
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}
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}
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break;
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}
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return CP_ACCESS_OK;
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}
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