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target/arm: Update ctr_el0_access for EL2
Update to include checks against HCR_EL2.TID2. Backports commit 97475a89375d62a7722e04ced9fbdf0b992f4b83 from qemu
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@ -5058,11 +5058,27 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
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static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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/* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
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* but the AArch32 CTR has its own reginfo struct)
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*/
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if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
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return CP_ACCESS_TRAP;
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int cur_el = arm_current_el(env);
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if (cur_el < 2) {
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uint64_t hcr = arm_hcr_el2_eff(env);
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if (cur_el == 0) {
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) {
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return CP_ACCESS_TRAP_EL2;
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}
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} else {
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if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
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return CP_ACCESS_TRAP;
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}
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if (hcr & HCR_TID2) {
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return CP_ACCESS_TRAP_EL2;
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}
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}
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} else if (hcr & HCR_TID2) {
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return CP_ACCESS_TRAP_EL2;
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}
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}
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if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) {
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