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target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR

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The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).

Backports 529577457cbba9e429af629c46204f63e50fa832
This commit is contained in:
Alex Richardson 2021-03-08 15:16:42 -05:00 committed by Lioncash
parent c50f8c9d93
commit 8e4e0a6993
1 changed files with 2 additions and 2 deletions
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4
qemu/target/riscv/cpu_bits.h
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@ -379,8 +379,8 @@
#define MSTATUS_MXR 0x00080000
#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
#define MSTATUS_GVA 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL