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target-i386: emulate LOCK'ed BTX ops using atomic helpers
Backports commit cfe819d309d472f75fd129faf1d1064a2498326c from qemu
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@ -7331,7 +7331,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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if (mod != 3) {
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s->rip_offset = 1;
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gen_lea_modrm(env, s, modrm);
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gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
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if (!(s->prefix & PREFIX_LOCK)) {
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gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
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}
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} else {
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gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm);
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}
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@ -7361,44 +7363,69 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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rm = (modrm & 7) | REX_B(s);
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gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T1, reg);
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if (mod != 3) {
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gen_lea_modrm(env, s, modrm);
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AddressParts a = gen_lea_modrm_0(env, s, modrm);
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/* specific case: we need to add a displacement */
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gen_exts(tcg_ctx, ot, cpu_T1);
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tcg_gen_sari_tl(tcg_ctx, cpu_tmp0, cpu_T1, 3 + ot);
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tcg_gen_shli_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, ot);
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tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_tmp0);
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gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
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tcg_gen_add_tl(tcg_ctx, cpu_A0, gen_lea_modrm_1(s, a), cpu_tmp0);
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gen_lea_v_seg(s, s->aflag, cpu_A0, a.def_seg, s->override);
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if (!(s->prefix & PREFIX_LOCK)) {
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gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
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}
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} else {
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gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm);
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}
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bt_op:
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tcg_gen_andi_tl(tcg_ctx, cpu_T1, cpu_T1, (1 << (3 + ot)) - 1);
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tcg_gen_shr_tl(tcg_ctx, cpu_tmp4, cpu_T0, cpu_T1);
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switch(op) {
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case 0:
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break;
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case 1:
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tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 1);
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tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, cpu_T1);
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tcg_gen_or_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0);
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break;
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case 2:
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tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 1);
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tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, cpu_T1);
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tcg_gen_andc_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0);
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break;
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default:
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case 3:
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tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 1);
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tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, cpu_T1);
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tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0);
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break;
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}
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if (op != 0) {
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if (mod != 3) {
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gen_op_st_v(s, ot, cpu_T0, cpu_A0);
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} else {
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gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0);
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tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 1);
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tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, cpu_T1);
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if (s->prefix & PREFIX_LOCK) {
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switch (op) {
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case 0: /* bt */
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/* Needs no atomic ops; we surpressed the normal
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memory load for LOCK above so do it now. */
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gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
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break;
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case 1: /* bts */
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tcg_gen_atomic_fetch_or_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_tmp0,
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s->mem_index, ot | MO_LE);
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break;
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case 2: /* btr */
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tcg_gen_not_tl(tcg_ctx, cpu_tmp0, cpu_tmp0);
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tcg_gen_atomic_fetch_and_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_tmp0,
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s->mem_index, ot | MO_LE);
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break;
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default:
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case 3: /* btc */
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tcg_gen_atomic_fetch_xor_tl(tcg_ctx, cpu_T0, cpu_A0, cpu_tmp0,
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s->mem_index, ot | MO_LE);
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break;
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}
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tcg_gen_shr_tl(tcg_ctx, cpu_tmp4, cpu_T0, cpu_T1);
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} else {
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tcg_gen_shr_tl(tcg_ctx, cpu_tmp4, cpu_T0, cpu_T1);
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switch (op) {
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case 0: /* bt */
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/* Data already loaded; nothing to do. */
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break;
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case 1: /* bts */
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tcg_gen_or_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0);
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break;
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case 2: /* btr */
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tcg_gen_andc_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0);
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break;
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default:
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case 3: /* btc */
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tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0);
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break;
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}
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if (op != 0) {
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if (mod != 3) {
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gen_op_st_v(s, ot, cpu_T0, cpu_A0);
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} else {
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gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0);
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}
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}
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}
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