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target-mips: correct MFC0 for CP0.EntryLo in MIPS64

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CP0.EntryLo bits 31:30 have to be cleared.

Backports commit b435f3f3d174721382b55bbd0c785ec50c1796a9 from qemu
This commit is contained in:
Leon Alrae 2018-02-13 13:35:42 -05:00 committed by Lioncash
parent 57f57a9de4
commit 907bb26e5f
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 6 deletions
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12
qemu/target-mips/translate.c
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@ -5029,10 +5029,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
/* Move RI/XI fields to bits 31:30 */
TCGv tmp = tcg_temp_new(tcg_ctx);
tcg_gen_andi_tl(tcg_ctx, tmp, arg, (3ull << CP0EnLo_XI));
tcg_gen_shri_tl(tcg_ctx, tmp, tmp, 32);
tcg_gen_or_tl(tcg_ctx, arg, arg, tmp);
tcg_gen_shri_tl(tcg_ctx, tmp, arg, CP0EnLo_XI);
tcg_gen_deposit_tl(tcg_ctx, arg, arg, tmp, 30, 2);
tcg_temp_free(tcg_ctx, tmp);
}
#endif
@ -5084,10 +5084,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
/* Move RI/XI fields to bits 31:30 */
TCGv tmp = tcg_temp_new(tcg_ctx);
tcg_gen_andi_tl(tcg_ctx, tmp, arg, (3ull << CP0EnLo_XI));
tcg_gen_shri_tl(tcg_ctx, tmp, tmp, 32);
tcg_gen_or_tl(tcg_ctx, arg, arg, tmp);
tcg_gen_shri_tl(tcg_ctx, tmp, arg, CP0EnLo_XI);
tcg_gen_deposit_tl(tcg_ctx, arg, arg, tmp, 30, 2);
tcg_temp_free(tcg_ctx, tmp);
}
#endif