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target/i386: Fix BLSR and BLSI

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The implementation of these two instructions was swapped.
At the same time, unify the setup of eflags for the insn group.

Backports commit 13672386a93fef64cfd33bd72fbf3d80f2c00e94 from qemu
This commit is contained in:
Richard Henderson 2018-07-03 01:21:56 -04:00 committed by Lioncash
parent 7ecf09a13d
commit 91359e67f9
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 20 deletions
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32
qemu/target/i386/translate.c
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@ -4620,34 +4620,26 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T0);
switch (reg & 7) {
case 1: /* blsr By,Ey */
tcg_gen_subi_tl(tcg_ctx, cpu_T1, cpu_T0, 1);
tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
break;
case 2: /* blsmsk By,Ey */
tcg_gen_subi_tl(tcg_ctx, cpu_T1, cpu_T0, 1);
tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
break;
case 3: /* blsi By, Ey */
tcg_gen_neg_tl(tcg_ctx, cpu_T1, cpu_T0);
tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
gen_op_mov_reg_v(tcg_ctx, ot, s->vex_v, cpu_T0);
gen_op_update2_cc(tcg_ctx);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
case 2: /* blsmsk By,Ey */
tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T0);
tcg_gen_subi_tl(tcg_ctx, cpu_T0, cpu_T0, 1);
tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_cc_src);
tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
case 3: /* blsi By, Ey */
tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T0);
tcg_gen_subi_tl(tcg_ctx, cpu_T0, cpu_T0, 1);
tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_cc_src);
tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
default:
goto unknown_op;
}
tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0);
gen_op_mov_reg_v(tcg_ctx, ot, s->vex_v, cpu_T0);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
default: