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target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)

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Backports commit b876452507d0b719cff0b478efafb34ac41db683 from qemu
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Soren Brinkmann 2018-02-17 13:04:42 -05:00 committed by Lioncash
parent 93386e2dd4
commit 9432e3a285
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1 changed files with 8 additions and 0 deletions
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8
qemu/target-arm/helper.c
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@ -2898,6 +2898,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },
{ "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[6]) },
{ "SPSR_IRQ", 0,4,3, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[4]) },
{ "SPSR_ABT", 0,4,3, 3,4,1, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[2]) },
{ "SPSR_UND", 0,4,3, 3,4,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[3]) },
{ "SPSR_FIQ", 0,4,3, 3,4,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[5]) },
{ "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_AA64,
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[2]), {0, 0},
NULL, NULL, vbar_write, },