target/riscv: Add the virtulisation mode

Backports commit ef6bb7b62682badefdcb744831510aaa5971684f from qemu

qemu/header_gen.py

@@ -5572,9 +5572,11 @@ riscv_symbols = (
     'riscv_cpu_register_types',
     'riscv_cpu_set_fflags',
     'riscv_cpu_set_mode',
+    'riscv_cpu_set_virt_enabled',
     'riscv_cpu_tlb_fill',
     'riscv_cpu_unassigned_access',
     'riscv_cpu_update_mip',
+    'riscv_cpu_virt_enabled',
     'riscv_csrrw',
     'riscv_csrrw_debug',
     'riscv_excp_names',

qemu/riscv32.h

@@ -3459,9 +3459,11 @@
 #define riscv_cpu_register_types riscv_cpu_register_types_riscv32
 #define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv32
 #define riscv_cpu_set_mode riscv_cpu_set_mode_riscv32
+#define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv32
 #define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv32
 #define riscv_cpu_unassigned_access riscv_cpu_unassigned_access_riscv32
 #define riscv_cpu_update_mip riscv_cpu_update_mip_riscv32
+#define riscv_cpu_virt_enabled riscv_cpu_virt_enabled_riscv32
 #define riscv_csrrw riscv_csrrw_riscv32
 #define riscv_csrrw_debug riscv_csrrw_debug_riscv32
 #define riscv_excp_names riscv_excp_names_riscv32

qemu/riscv64.h

@@ -3459,9 +3459,11 @@
 #define riscv_cpu_register_types riscv_cpu_register_types_riscv64
 #define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv64
 #define riscv_cpu_set_mode riscv_cpu_set_mode_riscv64
+#define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv64
 #define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv64
 #define riscv_cpu_unassigned_access riscv_cpu_unassigned_access_riscv64
 #define riscv_cpu_update_mip riscv_cpu_update_mip_riscv64
+#define riscv_cpu_virt_enabled riscv_cpu_virt_enabled_riscv64
 #define riscv_csrrw riscv_csrrw_riscv64
 #define riscv_csrrw_debug riscv_csrrw_debug_riscv64
 #define riscv_excp_names riscv_excp_names_riscv64

qemu/target/riscv/cpu.h

@@ -123,6 +123,8 @@ struct CPURISCVState {
 
 #ifndef CONFIG_USER_ONLY
     target_ulong priv;
+    /* This contains QEMU specific information about the virt state. */
+    target_ulong virt;
     target_ulong resetvec;
 
     target_ulong mhartid;
@@ -272,6 +274,8 @@ void riscv_cpu_do_interrupt(CPUState *cpu);
 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
+bool riscv_cpu_virt_enabled(CPURISCVState *env);
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

qemu/target/riscv/cpu_bits.h

@@ -431,6 +431,9 @@
 #define PRV_H 2 /* Reserved */
 #define PRV_M 3
 
+/* Virtulisation Register Fields */
+#define VIRT_ONOFF          1
+
 /* RV32 satp CSR field masks */
 #define SATP32_MODE         0x80000000
 #define SATP32_ASID         0x7fc00000

qemu/target/riscv/cpu_helper.c

@@ -72,6 +72,24 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 
 #if !defined(CONFIG_USER_ONLY)
 
+bool riscv_cpu_virt_enabled(CPURISCVState *env)
+{
+    if (!riscv_has_ext(env, RVH)) {
+        return false;
+    }
+
+    return get_field(env->virt, VIRT_ONOFF);
+}
+
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
+{
+    if (!riscv_has_ext(env, RVH)) {
+        return;
+    }
+
+    env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+}
+
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
 {
     CPURISCVState *env = &cpu->env;

qemu/target/riscv/unicorn.c

@@ -5,6 +5,7 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
+#include "fpu/softfloat.h"
 #include "hw/boards.h"
 #include "hw/riscv/spike.h"
 #include "sysemu/cpus.h"