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target/riscv: vector widening floating-point fused multiply-add instructions

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Backports 0dd509594fbd53fc9c3edc79bd7a575f079c3c87
This commit is contained in:
LIU Zhiwei 2021-03-07 11:37:21 -05:00 committed by Lioncash
parent 42116609f0
commit 95a6d78121
7 changed files with 174 additions and 0 deletions
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16
qemu/header_gen.py
View file

@ -7075,6 +7075,22 @@ riscv_symbols = (
'helper_vfnmsub_vf_h',
'helper_vfnmsub_vf_w',
'helper_vfnmsub_vf_d',
'helper_vfwmacc_vv_h',
'helper_vfwmacc_vv_w',
'helper_vfwnmacc_vv_h',
'helper_vfwnmacc_vv_w',
'helper_vfwmsac_vv_h',
'helper_vfwmsac_vv_w',
'helper_vfwnmsac_vv_h',
'helper_vfwnmsac_vv_w',
'helper_vfwmacc_vf_h',
'helper_vfwmacc_vf_w',
'helper_vfwnmacc_vf_h',
'helper_vfwnmacc_vf_w',
'helper_vfwmsac_vf_h',
'helper_vfwmsac_vf_w',
'helper_vfwnmsac_vf_h',
'helper_vfwnmsac_vf_w',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

16
qemu/riscv32.h
View file

@ -4511,6 +4511,22 @@
#define helper_vfnmsub_vf_h helper_vfnmsub_vf_h_riscv32
#define helper_vfnmsub_vf_w helper_vfnmsub_vf_w_riscv32
#define helper_vfnmsub_vf_d helper_vfnmsub_vf_d_riscv32
#define helper_vfwmacc_vv_h helper_vfwmacc_vv_h_riscv32
#define helper_vfwmacc_vv_w helper_vfwmacc_vv_w_riscv32
#define helper_vfwnmacc_vv_h helper_vfwnmacc_vv_h_riscv32
#define helper_vfwnmacc_vv_w helper_vfwnmacc_vv_w_riscv32
#define helper_vfwmsac_vv_h helper_vfwmsac_vv_h_riscv32
#define helper_vfwmsac_vv_w helper_vfwmsac_vv_w_riscv32
#define helper_vfwnmsac_vv_h helper_vfwnmsac_vv_h_riscv32
#define helper_vfwnmsac_vv_w helper_vfwnmsac_vv_w_riscv32
#define helper_vfwmacc_vf_h helper_vfwmacc_vf_h_riscv32
#define helper_vfwmacc_vf_w helper_vfwmacc_vf_w_riscv32
#define helper_vfwnmacc_vf_h helper_vfwnmacc_vf_h_riscv32
#define helper_vfwnmacc_vf_w helper_vfwnmacc_vf_w_riscv32
#define helper_vfwmsac_vf_h helper_vfwmsac_vf_h_riscv32
#define helper_vfwmsac_vf_w helper_vfwmsac_vf_w_riscv32
#define helper_vfwnmsac_vf_h helper_vfwnmsac_vf_h_riscv32
#define helper_vfwnmsac_vf_w helper_vfwnmsac_vf_w_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

16
qemu/riscv64.h
View file

@ -4511,6 +4511,22 @@
#define helper_vfnmsub_vf_h helper_vfnmsub_vf_h_riscv64
#define helper_vfnmsub_vf_w helper_vfnmsub_vf_w_riscv64
#define helper_vfnmsub_vf_d helper_vfnmsub_vf_d_riscv64
#define helper_vfwmacc_vv_h helper_vfwmacc_vv_h_riscv64
#define helper_vfwmacc_vv_w helper_vfwmacc_vv_w_riscv64
#define helper_vfwnmacc_vv_h helper_vfwnmacc_vv_h_riscv64
#define helper_vfwnmacc_vv_w helper_vfwnmacc_vv_w_riscv64
#define helper_vfwmsac_vv_h helper_vfwmsac_vv_h_riscv64
#define helper_vfwmsac_vv_w helper_vfwmsac_vv_w_riscv64
#define helper_vfwnmsac_vv_h helper_vfwnmsac_vv_h_riscv64
#define helper_vfwnmsac_vv_w helper_vfwnmsac_vv_w_riscv64
#define helper_vfwmacc_vf_h helper_vfwmacc_vf_h_riscv64
#define helper_vfwmacc_vf_w helper_vfwmacc_vf_w_riscv64
#define helper_vfwnmacc_vf_h helper_vfwnmacc_vf_h_riscv64
#define helper_vfwnmacc_vf_w helper_vfwnmacc_vf_w_riscv64
#define helper_vfwmsac_vf_h helper_vfwmsac_vf_h_riscv64
#define helper_vfwmsac_vf_w helper_vfwmsac_vf_w_riscv64
#define helper_vfwnmsac_vf_h helper_vfwnmsac_vf_h_riscv64
#define helper_vfwnmsac_vf_w helper_vfwnmsac_vf_w_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

17
qemu/target/riscv/helper.h
View file

@ -909,3 +909,20 @@ DEF_HELPER_6(vfmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfnmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfnmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfnmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)

8
qemu/target/riscv/insn32.decode
View file

@ -481,6 +481,14 @@ vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm
vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm
vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

10
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -2111,3 +2111,13 @@ GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)

91
qemu/target/riscv/vector_helper.c
View file

@ -3684,3 +3684,94 @@ RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
GEN_VEXT_VF(vfnmsub_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfnmsub_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfnmsub_vf_d, 8, 8, clearq)
/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
float16_to_float32(b, true, s), d, 0, s);
}
static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
float32_to_float64(b, s), d, 0, s);
}
RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32)
GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4, clearl)
GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8, clearq)
RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16)
RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
GEN_VEXT_VF(vfwmacc_vf_h, 2, 4, clearl)
GEN_VEXT_VF(vfwmacc_vf_w, 4, 8, clearq)
static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
float16_to_float32(b, true, s), d,
float_muladd_negate_c | float_muladd_negate_product, s);
}
static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
float32_to_float64(b, s), d,
float_muladd_negate_c | float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32)
GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4, clearl)
GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8, clearq)
RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16)
RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32)
GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4, clearl)
GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8, clearq)
static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
float16_to_float32(b, true, s), d,
float_muladd_negate_c, s);
}
static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
float32_to_float64(b, s), d,
float_muladd_negate_c, s);
}
RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32)
GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4, clearl)
GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8, clearq)
RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16)
RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32)
GEN_VEXT_VF(vfwmsac_vf_h, 2, 4, clearl)
GEN_VEXT_VF(vfwmsac_vf_w, 4, 8, clearq)
static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
float16_to_float32(b, true, s), d,
float_muladd_negate_product, s);
}
static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
float32_to_float64(b, s), d,
float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32)
GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4, clearl)
GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8, clearq)
RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16)
RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32)
GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4, clearl)
GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8, clearq)