yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-22 13:51:11 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/mips: Clean up handling of CP0 register 6

Browse source 
Clean up handling of CP0 register 6.

Backports commit 9023594b4081585518faf9b144bce62067381990 from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 22:54:24 -05:00 committed by Lioncash
parent 49eeba113e
commit 95fa7aae61
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 34 additions and 28 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
qemu/target/mips/cpu.h
View file

@ -320,6 +320,12 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
#define CP0_REG06__SRSCONF0 1
#define CP0_REG06__SRSCONF1 2
#define CP0_REG06__SRSCONF2 3
#define CP0_REG06__SRSCONF3 4
#define CP0_REG06__SRSCONF4 5
#define CP0_REG06__PWCTL 6
/* CP0 Register 07 */
#define CP0_REG07__HWRENA 0
/* CP0 Register 08 */

56
qemu/target/mips/translate.c
View file

@ -7128,36 +7128,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
case 0:
case CP0_REG06__WIRED:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
case 1:
case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
case 2:
case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
case 3:
case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
case 4:
case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
case 5:
case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
case 6:
case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@ -7858,36 +7858,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
case 0:
case CP0_REG06__WIRED:
gen_helper_mtc0_wired(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Wired";
break;
case 1:
case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf0";
break;
case 2:
case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf1";
break;
case 3:
case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf2";
break;
case 4:
case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf3";
break;
case 5:
case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf4";
break;
case 6:
case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PWCtl";
@ -8598,36 +8598,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
case 0:
case CP0_REG06__WIRED:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
case 1:
case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
case 2:
case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
case 3:
case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
case 4:
case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
case 5:
case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
case 6:
case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@ -9310,36 +9310,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
case 0:
case CP0_REG06__WIRED:
gen_helper_mtc0_wired(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Wired";
break;
case 1:
case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf0";
break;
case 2:
case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf1";
break;
case 3:
case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf2";
break;
case 4:
case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf3";
break;
case 5:
case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SRSConf4";
break;
case 6:
case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PWCtl";