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target/arm: Fix neon VTBL/VTBX for len > 1
The helper function did not get updated when we reorganized the vector register file for SVE. Since then, the neon dregs are non-sequential and cannot be simply indexed. At the same time, make the helper function operate on 64-bit quantities so that we do not have to call it twice. Backports 604cef3e57eaeeef77074d78f6cf2eca1be11c62
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@ -243,7 +243,7 @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
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DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
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DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
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DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
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DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
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DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
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DEF_HELPER_3(shl_cc, i32, env, i32, i32)
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DEF_HELPER_3(shr_cc, i32, env, i32, i32)
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@ -68,21 +68,24 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
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cpu_loop_exit_restore(cs, ra);
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}
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uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
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uint32_t maxindex)
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uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
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uint64_t ireg, uint64_t def)
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{
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uint32_t val, shift;
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uint64_t *table = vn;
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uint64_t tmp, val = 0;
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uint32_t maxindex = ((desc & 3) + 1) * 8;
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uint32_t base_reg = desc >> 2;
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uint32_t shift, index, reg;
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val = 0;
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for (shift = 0; shift < 32; shift += 8) {
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uint32_t index = (ireg >> shift) & 0xff;
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for (shift = 0; shift < 64; shift += 8) {
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index = (ireg >> shift) & 0xff;
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if (index < maxindex) {
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uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
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val |= tmp << shift;
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reg = base_reg + (index >> 3);
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tmp = *aa32_vfp_dreg(env, reg);
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tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
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} else {
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val |= def & (0xff << shift);
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tmp = def & (0xffull << shift);
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}
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val |= tmp;
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}
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return val;
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}
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@ -2903,9 +2903,8 @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
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static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int n;
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TCGv_i32 tmp, tmp2, tmp3, tmp4;
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TCGv_ptr ptr1;
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TCGv_i64 val, def;
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TCGv_i32 desc;
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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@ -2921,43 +2920,30 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
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return true;
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}
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n = a->len + 1;
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if ((a->vn + n) > 32) {
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if ((a->vn + a->len + 1) > 32) {
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/*
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* This is UNPREDICTABLE; we choose to UNDEF to avoid the
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* helper function running off the end of the register file.
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*/
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return false;
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}
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n <<= 3;
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tmp = tcg_temp_new_i32(tcg_ctx);
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if (a->op) {
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read_neon_element32(s, tmp, a->vd, 0, MO_32);
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} else {
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tcg_gen_movi_i32(tcg_ctx, tmp, 0);
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}
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tmp2 = tcg_temp_new_i32(tcg_ctx);
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read_neon_element32(s, tmp2, a->vm, 0, MO_32);
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ptr1 = vfp_reg_ptr(s, true, a->vn);
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tmp4 = tcg_const_i32(tcg_ctx, n);
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gen_helper_neon_tbl(tcg_ctx, tmp2, tmp2, tmp, ptr1, tmp4);
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desc = tcg_const_i32(tcg_ctx, (a->vn << 2) | a->len);
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def = tcg_temp_new_i64(tcg_ctx);
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if (a->op) {
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read_neon_element32(s, tmp, a->vd, 1, MO_32);
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read_neon_element64(s, def, a->vd, 0, MO_64);
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} else {
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tcg_gen_movi_i32(tcg_ctx, tmp, 0);
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tcg_gen_movi_i64(tcg_ctx, def, 0);
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}
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tmp3 = tcg_temp_new_i32(tcg_ctx);
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read_neon_element32(s, tmp3, a->vm, 1, MO_32);
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gen_helper_neon_tbl(tcg_ctx, tmp3, tmp3, tmp, ptr1, tmp4);
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tcg_temp_free_i32(tcg_ctx, tmp);
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tcg_temp_free_i32(tcg_ctx, tmp4);
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tcg_temp_free_ptr(tcg_ctx, ptr1);
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val = tcg_temp_new_i64(tcg_ctx);
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read_neon_element64(s, val, a->vm, 0, MO_64);
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write_neon_element32(s, tmp2, a->vd, 0, MO_32);
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write_neon_element32(s, tmp3, a->vd, 1, MO_32);
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tcg_temp_free_i32(tcg_ctx, tmp2);
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tcg_temp_free_i32(tcg_ctx, tmp3);
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gen_helper_neon_tbl(tcg_ctx, val, tcg_ctx->cpu_env, desc, val, def);
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write_neon_element64(s, val, a->vd, 0, MO_64);
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tcg_temp_free_i64(tcg_ctx, def);
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tcg_temp_free_i64(tcg_ctx, val);
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tcg_temp_free_i32(tcg_ctx, desc);
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return true;
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}
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