target/arm: Introduce arm_mmu_idx

The pattern

ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));

is computing the full ARMMMUIdx, stripping off the ARM bits,
and then putting them back.

Avoid the extra two steps with the appropriate helper function.

Backports commit 50494a279dab22a015aba9501a94fcc3cd52140e from qemu

qemu/aarch64.h

@@ -3283,6 +3283,7 @@
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64
 #define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64
+#define arm_mmu_idx arm_mmu_idx_aarch64
 #define arm_regime_tbi0 arm_regime_tbi0_aarch64
 #define arm_regime_tbi1 arm_regime_tbi1_aarch64
 #define arm_register_pre_el_change_hook arm_register_pre_el_change_hook_aarch64

qemu/aarch64eb.h

@@ -3283,6 +3283,7 @@
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64eb
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64eb
 #define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64eb
+#define arm_mmu_idx arm_mmu_idx_aarch64eb
 #define arm_regime_tbi0 arm_regime_tbi0_aarch64eb
 #define arm_regime_tbi1 arm_regime_tbi1_aarch64eb
 #define arm_register_pre_el_change_hook arm_register_pre_el_change_hook_aarch64eb

qemu/arm.h

@@ -3275,6 +3275,7 @@
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_arm
 #define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm
 #define arm_hcr_el2_eff arm_hcr_el2_eff_arm
+#define arm_mmu_idx arm_mmu_idx_arm
 #define arm_regime_tbi0 arm_regime_tbi0_arm
 #define arm_regime_tbi1 arm_regime_tbi1_arm
 #define arm_register_pre_el_change_hook arm_register_pre_el_change_hook_arm

qemu/armeb.h

@@ -3275,6 +3275,7 @@
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_armeb
 #define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb
 #define arm_hcr_el2_eff arm_hcr_el2_eff_armeb
+#define arm_mmu_idx arm_mmu_idx_armeb
 #define arm_regime_tbi0 arm_regime_tbi0_armeb
 #define arm_regime_tbi1 arm_regime_tbi1_armeb
 #define arm_register_pre_el_change_hook arm_register_pre_el_change_hook_armeb

qemu/header_gen.py

@@ -3284,6 +3284,7 @@ arm_symbols = (
     'arm_v7m_mmu_idx_for_secstate_and_priv',
     'ARM_REGS_STORAGE_SIZE',
     'arm_hcr_el2_eff',
+    'arm_mmu_idx',
     'arm_regime_tbi0',
     'arm_regime_tbi1',
     'arm_register_pre_el_change_hook',
@@ -3320,6 +3321,7 @@ aarch64_symbols = (
     'arm_v7m_mmu_idx_for_secstate',
     'arm_v7m_mmu_idx_for_secstate_and_priv',
     'arm_hcr_el2_eff',
+    'arm_mmu_idx',
     'arm_regime_tbi0',
     'arm_regime_tbi1',
     'arm_register_pre_el_change_hook',

qemu/target/arm/cpu.h

@@ -2738,7 +2738,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
 /* Return the MMU index for a v7M CPU in the specified security state */
 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
 
-/* Determine the current mmu_idx to use for normal loads/stores */
+/**
+ * cpu_mmu_index:
+ * @env: The cpu environment
+ * @ifetch: True for code access, false for data access.
+ *
+ * Return the core mmu index for the current translation regime.
+ * This function is used by generic TCG code paths.
+ */
 int cpu_mmu_index(CPUARMState *env, bool ifetch);
 
 /* Indexes used when registering address spaces with cpu_address_space_init */

qemu/target/arm/helper.c

@@ -6302,7 +6302,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
             limit = env->v7m.msplim[M_REG_S];
         }
     } else {
-        mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
+        mmu_idx = arm_mmu_idx(env);
         frame_sp_p = &env->regs[13];
         limit = v7m_sp_limit(env);
     }
@@ -6480,7 +6480,7 @@ static bool v7m_push_stack(ARMCPU *cpu)
     CPUARMState *env = &cpu->env;
     uint32_t xpsr = xpsr_read(env);
     uint32_t frameptr = env->regs[13];
-    ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
+    ARMMMUIdx mmu_idx = arm_mmu_idx(env);
 
     /* Align stack pointer if the guest wants that */
     if ((frameptr & 4) &&
@@ -10250,7 +10250,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
     int prot;
     bool ret;
     ARMMMUFaultInfo fi = {0};
-    ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
+    ARMMMUIdx mmu_idx = arm_mmu_idx(env);
 
     ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
                         attrs, &prot, &page_size, &fi, NULL);
@@ -12184,20 +12184,25 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
 }
 
-int cpu_mmu_index(CPUARMState *env, bool ifetch)
+ARMMMUIdx arm_mmu_idx(CPUARMState *env)
 {
-    int el = arm_current_el(env);
+    int el;
 
     if (arm_feature(env, ARM_FEATURE_M)) {
-        ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
-
-        return arm_to_core_mmu_idx(mmu_idx);
+        return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
     }
 
+    el = arm_current_el(env);
     if (el < 2 && arm_is_secure_below_el3(env)) {
-        return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
+        return ARMMMUIdx_S1SE0 + el;
+    } else {
+        return ARMMMUIdx_S12NSE0 + el;
     }
-    return el;
+}
+
+int cpu_mmu_index(CPUARMState *env, bool ifetch)
+{
+    return arm_to_core_mmu_idx(arm_mmu_idx(env));
 }
 
 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

qemu/target/arm/internals.h

@@ -921,4 +921,12 @@ void arm_cpu_update_virq(ARMCPU *cpu);
  */
 void arm_cpu_update_vfiq(ARMCPU *cpu);
 
+/**
+ * arm_mmu_idx:
+ * @env: The cpu environment
+ *
+ * Return the full ARMMMUIdx for the current translation regime.
+ */
+ARMMMUIdx arm_mmu_idx(CPUARMState *env);
+
 #endif