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target/riscv: vector widening integer multiply-add instructions

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Backports 2b587b335050dbc0cb3823758341f145c0375312
This commit is contained in:
LIU Zhiwei 2021-03-05 09:13:01 -05:00 committed by Lioncash
parent 58891e213d
commit 9d14cc8d35
7 changed files with 146 additions and 0 deletions
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21
qemu/header_gen.py
View file

@ -6805,6 +6805,27 @@ riscv_symbols = (
'helper_vnmsub_vx_h',
'helper_vnmsub_vx_w',
'helper_vnmsub_vx_d',
'helper_vwmaccu_vv_b',
'helper_vwmaccu_vv_h',
'helper_vwmaccu_vv_w',
'helper_vwmacc_vv_b',
'helper_vwmacc_vv_h',
'helper_vwmacc_vv_w',
'helper_vwmaccsu_vv_b',
'helper_vwmaccsu_vv_h',
'helper_vwmaccsu_vv_w',
'helper_vwmaccu_vx_b',
'helper_vwmaccu_vx_h',
'helper_vwmaccu_vx_w',
'helper_vwmacc_vx_b',
'helper_vwmacc_vx_h',
'helper_vwmacc_vx_w',
'helper_vwmaccsu_vx_b',
'helper_vwmaccsu_vx_h',
'helper_vwmaccsu_vx_w',
'helper_vwmaccus_vx_b',
'helper_vwmaccus_vx_h',
'helper_vwmaccus_vx_w',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

21
qemu/riscv32.h
View file

@ -4241,6 +4241,27 @@
#define helper_vnmsub_vx_h helper_vnmsub_vx_h_riscv32
#define helper_vnmsub_vx_w helper_vnmsub_vx_w_riscv32
#define helper_vnmsub_vx_d helper_vnmsub_vx_d_riscv32
#define helper_vwmaccu_vv_b helper_vwmaccu_vv_b_riscv32
#define helper_vwmaccu_vv_h helper_vwmaccu_vv_h_riscv32
#define helper_vwmaccu_vv_w helper_vwmaccu_vv_w_riscv32
#define helper_vwmacc_vv_b helper_vwmacc_vv_b_riscv32
#define helper_vwmacc_vv_h helper_vwmacc_vv_h_riscv32
#define helper_vwmacc_vv_w helper_vwmacc_vv_w_riscv32
#define helper_vwmaccsu_vv_b helper_vwmaccsu_vv_b_riscv32
#define helper_vwmaccsu_vv_h helper_vwmaccsu_vv_h_riscv32
#define helper_vwmaccsu_vv_w helper_vwmaccsu_vv_w_riscv32
#define helper_vwmaccu_vx_b helper_vwmaccu_vx_b_riscv32
#define helper_vwmaccu_vx_h helper_vwmaccu_vx_h_riscv32
#define helper_vwmaccu_vx_w helper_vwmaccu_vx_w_riscv32
#define helper_vwmacc_vx_b helper_vwmacc_vx_b_riscv32
#define helper_vwmacc_vx_h helper_vwmacc_vx_h_riscv32
#define helper_vwmacc_vx_w helper_vwmacc_vx_w_riscv32
#define helper_vwmaccsu_vx_b helper_vwmaccsu_vx_b_riscv32
#define helper_vwmaccsu_vx_h helper_vwmaccsu_vx_h_riscv32
#define helper_vwmaccsu_vx_w helper_vwmaccsu_vx_w_riscv32
#define helper_vwmaccus_vx_b helper_vwmaccus_vx_b_riscv32
#define helper_vwmaccus_vx_h helper_vwmaccus_vx_h_riscv32
#define helper_vwmaccus_vx_w helper_vwmaccus_vx_w_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

21
qemu/riscv64.h
View file

@ -4241,6 +4241,27 @@
#define helper_vnmsub_vx_h helper_vnmsub_vx_h_riscv64
#define helper_vnmsub_vx_w helper_vnmsub_vx_w_riscv64
#define helper_vnmsub_vx_d helper_vnmsub_vx_d_riscv64
#define helper_vwmaccu_vv_b helper_vwmaccu_vv_b_riscv64
#define helper_vwmaccu_vv_h helper_vwmaccu_vv_h_riscv64
#define helper_vwmaccu_vv_w helper_vwmaccu_vv_w_riscv64
#define helper_vwmacc_vv_b helper_vwmacc_vv_b_riscv64
#define helper_vwmacc_vv_h helper_vwmacc_vv_h_riscv64
#define helper_vwmacc_vv_w helper_vwmacc_vv_w_riscv64
#define helper_vwmaccsu_vv_b helper_vwmaccsu_vv_b_riscv64
#define helper_vwmaccsu_vv_h helper_vwmaccsu_vv_h_riscv64
#define helper_vwmaccsu_vv_w helper_vwmaccsu_vv_w_riscv64
#define helper_vwmaccu_vx_b helper_vwmaccu_vx_b_riscv64
#define helper_vwmaccu_vx_h helper_vwmaccu_vx_h_riscv64
#define helper_vwmaccu_vx_w helper_vwmaccu_vx_w_riscv64
#define helper_vwmacc_vx_b helper_vwmacc_vx_b_riscv64
#define helper_vwmacc_vx_h helper_vwmacc_vx_h_riscv64
#define helper_vwmacc_vx_w helper_vwmacc_vx_w_riscv64
#define helper_vwmaccsu_vx_b helper_vwmaccsu_vx_b_riscv64
#define helper_vwmaccsu_vx_h helper_vwmaccsu_vx_h_riscv64
#define helper_vwmaccsu_vx_w helper_vwmaccsu_vx_w_riscv64
#define helper_vwmaccus_vx_b helper_vwmaccus_vx_b_riscv64
#define helper_vwmaccus_vx_h helper_vwmaccus_vx_h_riscv64
#define helper_vwmaccus_vx_w helper_vwmaccus_vx_w_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

22
qemu/target/riscv/helper.h
View file

@ -643,3 +643,25 @@ DEF_HELPER_6(vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)

7
qemu/target/riscv/insn32.decode
View file

@ -389,6 +389,13 @@ vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

9
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -1540,3 +1540,12 @@ GEN_OPIVX_TRANS(vmacc_vx, opivx_check)
GEN_OPIVX_TRANS(vnmsac_vx, opivx_check)
GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
/* Vector Widening Integer Multiply-Add Instructions */
GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)

45
qemu/target/riscv/vector_helper.c
View file

@ -1966,3 +1966,48 @@ GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq)
/* Vector Widening Integer Multiply-Add Instructions */
RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC)
RVVCALL(OPIVV3, vwmaccu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MACC)
RVVCALL(OPIVV3, vwmaccu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MACC)
RVVCALL(OPIVV3, vwmacc_vv_b, WOP_SSS_B, H2, H1, H1, DO_MACC)
RVVCALL(OPIVV3, vwmacc_vv_h, WOP_SSS_H, H4, H2, H2, DO_MACC)
RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC)
RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC)
RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC)
RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC)
GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh)
GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl)
GEN_VEXT_VV(vwmaccu_vv_w, 4, 8, clearq)
GEN_VEXT_VV(vwmacc_vv_b, 1, 2, clearh)
GEN_VEXT_VV(vwmacc_vv_h, 2, 4, clearl)
GEN_VEXT_VV(vwmacc_vv_w, 4, 8, clearq)
GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2, clearh)
GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4, clearl)
GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8, clearq)
RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC)
RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC)
RVVCALL(OPIVX3, vwmaccu_vx_w, WOP_UUU_W, H8, H4, DO_MACC)
RVVCALL(OPIVX3, vwmacc_vx_b, WOP_SSS_B, H2, H1, DO_MACC)
RVVCALL(OPIVX3, vwmacc_vx_h, WOP_SSS_H, H4, H2, DO_MACC)
RVVCALL(OPIVX3, vwmacc_vx_w, WOP_SSS_W, H8, H4, DO_MACC)
RVVCALL(OPIVX3, vwmaccsu_vx_b, WOP_SSU_B, H2, H1, DO_MACC)
RVVCALL(OPIVX3, vwmaccsu_vx_h, WOP_SSU_H, H4, H2, DO_MACC)
RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC)
RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC)
RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC)
RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC)
GEN_VEXT_VX(vwmaccu_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmaccu_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmaccu_vx_w, 4, 8, clearq)
GEN_VEXT_VX(vwmacc_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmacc_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmacc_vx_w, 4, 8, clearq)
GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq)
GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq)