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arm: Add ARMv6-M programmer's model support

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Forbid stack alignment change. (CCR)
Reserve FAULTMASK, BASEPRI registers.
Report any fault as a HardFault. Disable MemManage, BusFault and
UsageFault, so they always escalated to HardFault. (SHCSR)

Backports commit 22ab3460017cfcfb6b50f05838ad142e08becce5 from qemu
This commit is contained in:
Julia Suvorova 2018-08-16 06:36:25 -04:00 committed by Lioncash
parent b67b948feb
commit 9d7deb2997
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 15 additions and 2 deletions
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4
qemu/target/arm/cpu.c
View file

@ -222,6 +222,10 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
} }
if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
}
/* Unlike A/R profile, M profile defines the reset LR value */ /* Unlike A/R profile, M profile defines the reset LR value */
env->regs[14] = 0xffffffff; env->regs[14] = 0xffffffff;

13
qemu/target/arm/helper.c
View file

@ -9915,13 +9915,13 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.primask[M_REG_NS] = val & 1; env->v7m.primask[M_REG_NS] = val & 1;
return; return;
case 0x91: /* BASEPRI_NS */ case 0x91: /* BASEPRI_NS */
if (!env->v7m.secure) { if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) {
return; return;
} }
env->v7m.basepri[M_REG_NS] = val & 0xff; env->v7m.basepri[M_REG_NS] = val & 0xff;
return; return;
case 0x93: /* FAULTMASK_NS */ case 0x93: /* FAULTMASK_NS */
if (!env->v7m.secure) { if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) {
return; return;
} }
env->v7m.faultmask[M_REG_NS] = val & 1; env->v7m.faultmask[M_REG_NS] = val & 1;
@ -10012,9 +10012,15 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.primask[env->v7m.secure] = val & 1; env->v7m.primask[env->v7m.secure] = val & 1;
break; break;
case 17: /* BASEPRI */ case 17: /* BASEPRI */
if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
goto bad_reg;
}
env->v7m.basepri[env->v7m.secure] = val & 0xff; env->v7m.basepri[env->v7m.secure] = val & 0xff;
break; break;
case 18: /* BASEPRI_MAX */ case 18: /* BASEPRI_MAX */
if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
goto bad_reg;
}
val &= 0xff; val &= 0xff;
if (val != 0 && (val < env->v7m.basepri[env->v7m.secure] if (val != 0 && (val < env->v7m.basepri[env->v7m.secure]
|| env->v7m.basepri[env->v7m.secure] == 0)) { || env->v7m.basepri[env->v7m.secure] == 0)) {
@ -10022,6 +10028,9 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
} }
break; break;
case 19: /* FAULTMASK */ case 19: /* FAULTMASK */
if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
goto bad_reg;
}
env->v7m.faultmask[env->v7m.secure] = val & 1; env->v7m.faultmask[env->v7m.secure] = val & 1;
break; break;
case 20: /* CONTROL */ case 20: /* CONTROL */