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target/mips: Clean up handling of CP0 register 27

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Clean up handling of CP0 register 27.

Backports commit 5a10873d7ddd5d84c38c6f0dd69116b93219a7c1 from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 23:37:58 -05:00 committed by Lioncash
parent 9fe6520144
commit 9ed9ff06ab
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 16 deletions
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20
qemu/target/mips/translate.c
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@ -7545,10 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case CP0_REG27__CACHERR:
tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@ -8304,10 +8301,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
@ -9031,10 +9025,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_27:
switch (sel) {
/* ignored */
case 0:
case 1:
case 2:
case 3:
case CP0_REG27__CACHERR:
tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@ -9767,10 +9758,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;