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tcg: Add deposit_z expander

Browse source 
While we don't require a new opcode, it is handy to have an expander
that knows the first source is zero.

Backports commit 07cc68d52852bf47dea7c402b46ddd28248d4212 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 13:28:18 -05:00 committed by Lioncash
parent 8e0585dcb1
commit 9f2fcaaf27
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
16 changed files with 181 additions and 2 deletions
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2
qemu/aarch64.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_aarch64
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_aarch64
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_aarch64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_aarch64
#define tcg_gen_div_i32 tcg_gen_div_i32_aarch64
#define tcg_gen_div_i64 tcg_gen_div_i64_aarch64

2
qemu/aarch64eb.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64eb
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64eb
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_aarch64eb
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_aarch64eb
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_aarch64eb
#define tcg_gen_discard_i64 tcg_gen_discard_i64_aarch64eb
#define tcg_gen_div_i32 tcg_gen_div_i32_aarch64eb
#define tcg_gen_div_i64 tcg_gen_div_i64_aarch64eb

2
qemu/arm.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_arm
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_arm
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_arm
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_arm
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_arm
#define tcg_gen_discard_i64 tcg_gen_discard_i64_arm
#define tcg_gen_div_i32 tcg_gen_div_i32_arm
#define tcg_gen_div_i64 tcg_gen_div_i64_arm

2
qemu/armeb.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_armeb
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_armeb
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_armeb
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_armeb
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_armeb
#define tcg_gen_discard_i64 tcg_gen_discard_i64_armeb
#define tcg_gen_div_i32 tcg_gen_div_i32_armeb
#define tcg_gen_div_i64 tcg_gen_div_i64_armeb

2
qemu/header_gen.py
View file

@ -3017,6 +3017,8 @@ symbols = (
'tcg_gen_concat_i32_i64',
'tcg_gen_deposit_i32',
'tcg_gen_deposit_i64',
'tcg_gen_deposit_z_i32',
'tcg_gen_deposit_z_i64',
'tcg_gen_discard_i64',
'tcg_gen_div_i32',
'tcg_gen_div_i64',

2
qemu/m68k.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_m68k
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_m68k
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_m68k
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_m68k
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_m68k
#define tcg_gen_discard_i64 tcg_gen_discard_i64_m68k
#define tcg_gen_div_i32 tcg_gen_div_i32_m68k
#define tcg_gen_div_i64 tcg_gen_div_i64_m68k

2
qemu/mips.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_mips
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_mips
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips
#define tcg_gen_div_i32 tcg_gen_div_i32_mips
#define tcg_gen_div_i64 tcg_gen_div_i64_mips

2
qemu/mips64.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips64
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_mips64
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_mips64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips64
#define tcg_gen_div_i32 tcg_gen_div_i32_mips64
#define tcg_gen_div_i64 tcg_gen_div_i64_mips64

2
qemu/mips64el.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64el
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64el
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips64el
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_mips64el
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_mips64el
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips64el
#define tcg_gen_div_i32 tcg_gen_div_i32_mips64el
#define tcg_gen_div_i64 tcg_gen_div_i64_mips64el

2
qemu/mipsel.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mipsel
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mipsel
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mipsel
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_mipsel
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_mipsel
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mipsel
#define tcg_gen_div_i32 tcg_gen_div_i32_mipsel
#define tcg_gen_div_i64 tcg_gen_div_i64_mipsel

2
qemu/powerpc.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_powerpc
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_powerpc
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_powerpc
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_powerpc
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_powerpc
#define tcg_gen_discard_i64 tcg_gen_discard_i64_powerpc
#define tcg_gen_div_i32 tcg_gen_div_i32_powerpc
#define tcg_gen_div_i64 tcg_gen_div_i64_powerpc

2
qemu/sparc.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_sparc
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_sparc
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_sparc
#define tcg_gen_discard_i64 tcg_gen_discard_i64_sparc
#define tcg_gen_div_i32 tcg_gen_div_i32_sparc
#define tcg_gen_div_i64 tcg_gen_div_i64_sparc

2
qemu/sparc64.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_sparc64
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_sparc64
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_sparc64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_sparc64
#define tcg_gen_div_i32 tcg_gen_div_i32_sparc64
#define tcg_gen_div_i64 tcg_gen_div_i64_sparc64

149
qemu/tcg/tcg-op.c
View file

@ -532,10 +532,11 @@ void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar
TCGv_i32 t1;
tcg_debug_assert(ofs < 32);
tcg_debug_assert(len > 0);
tcg_debug_assert(len <= 32);
tcg_debug_assert(ofs + len <= 32);
if (ofs == 0 && len == 32) {
if (len == 32) {
tcg_gen_mov_i32(s, ret, arg2);
return;
}
@ -559,6 +560,64 @@ void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar
tcg_temp_free_i32(s, t1);
}
void tcg_gen_deposit_z_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len)
{
tcg_debug_assert(ofs < 32);
tcg_debug_assert(len > 0);
tcg_debug_assert(len <= 32);
tcg_debug_assert(ofs + len <= 32);
if (ofs + len == 32) {
tcg_gen_shli_i32(s, ret, arg, ofs);
} else if (ofs == 0) {
tcg_gen_andi_i32(s, ret, arg, (1u << len) - 1);
} else if (TCG_TARGET_HAS_deposit_i32
&& TCG_TARGET_deposit_i32_valid(ofs, len)) {
TCGv_i32 zero = tcg_const_i32(s, 0);
tcg_gen_op5ii_i32(s, INDEX_op_deposit_i32, ret, zero, arg, ofs, len);
tcg_temp_free_i32(s, zero);
} else {
/* To help two-operand hosts we prefer to zero-extend first,
which allows ARG to stay live. */
switch (len) {
case 16:
if (TCG_TARGET_HAS_ext16u_i32) {
tcg_gen_ext16u_i32(s, ret, arg);
tcg_gen_shli_i32(s, ret, ret, ofs);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8u_i32) {
tcg_gen_ext8u_i32(s, ret, arg);
tcg_gen_shli_i32(s, ret, ret, ofs);
return;
}
break;
}
/* Otherwise prefer zero-extension over AND for code size. */
switch (ofs + len) {
case 16:
if (TCG_TARGET_HAS_ext16u_i32) {
tcg_gen_shli_i32(s, ret, arg, ofs);
tcg_gen_ext16u_i32(s, ret, ret);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8u_i32) {
tcg_gen_shli_i32(s, ret, arg, ofs);
tcg_gen_ext8u_i32(s, ret, ret);
return;
}
break;
}
tcg_gen_andi_i32(s, ret, arg, (1u << len) - 1);
tcg_gen_shli_i32(s, ret, ret, ofs);
}
}
void tcg_gen_extract_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len)
{
@ -1724,10 +1783,11 @@ void tcg_gen_deposit_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 ar
TCGv_i64 t1;
tcg_debug_assert(ofs < 64);
tcg_debug_assert(len > 0);
tcg_debug_assert(len <= 64);
tcg_debug_assert(ofs + len <= 64);
if (ofs == 0 && len == 64) {
if (len == 64) {
tcg_gen_mov_i64(s, ret, arg2);
return;
}
@ -1766,6 +1826,91 @@ void tcg_gen_deposit_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 ar
tcg_temp_free_i64(s, t1);
}
void tcg_gen_deposit_z_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len)
{
tcg_debug_assert(ofs < 64);
tcg_debug_assert(len > 0);
tcg_debug_assert(len <= 64);
tcg_debug_assert(ofs + len <= 64);
if (ofs + len == 64) {
tcg_gen_shli_i64(s, ret, arg, ofs);
} else if (ofs == 0) {
tcg_gen_andi_i64(s, ret, arg, (1ull << len) - 1);
} else if (TCG_TARGET_HAS_deposit_i64
&& TCG_TARGET_deposit_i64_valid(ofs, len)) {
TCGv_i64 zero = tcg_const_i64(s, 0);
tcg_gen_op5ii_i64(s, INDEX_op_deposit_i64, ret, zero, arg, ofs, len);
tcg_temp_free_i64(s, zero);
} else {
if (TCG_TARGET_REG_BITS == 32) {
if (ofs >= 32) {
tcg_gen_deposit_z_i32(s, TCGV_HIGH(ret), TCGV_LOW(arg),
ofs - 32, len);
tcg_gen_movi_i32(s, TCGV_LOW(ret), 0);
return;
}
if (ofs + len <= 32) {
tcg_gen_deposit_z_i32(s, TCGV_LOW(ret), TCGV_LOW(arg), ofs, len);
tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0);
return;
}
}
/* To help two-operand hosts we prefer to zero-extend first,
which allows ARG to stay live. */
switch (len) {
case 32:
if (TCG_TARGET_HAS_ext32u_i64) {
tcg_gen_ext32u_i64(s, ret, arg);
tcg_gen_shli_i64(s, ret, ret, ofs);
return;
}
break;
case 16:
if (TCG_TARGET_HAS_ext16u_i64) {
tcg_gen_ext16u_i64(s, ret, arg);
tcg_gen_shli_i64(s, ret, ret, ofs);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8u_i64) {
tcg_gen_ext8u_i64(s, ret, arg);
tcg_gen_shli_i64(s, ret, ret, ofs);
return;
}
break;
}
/* Otherwise prefer zero-extension over AND for code size. */
switch (ofs + len) {
case 32:
if (TCG_TARGET_HAS_ext32u_i64) {
tcg_gen_shli_i64(s, ret, arg, ofs);
tcg_gen_ext32u_i64(s, ret, ret);
return;
}
break;
case 16:
if (TCG_TARGET_HAS_ext16u_i64) {
tcg_gen_shli_i64(s, ret, arg, ofs);
tcg_gen_ext16u_i64(s, ret, ret);
return;
}
break;
case 8:
if (TCG_TARGET_HAS_ext8u_i64) {
tcg_gen_shli_i64(s, ret, arg, ofs);
tcg_gen_ext8u_i64(s, ret, ret);
return;
}
break;
}
tcg_gen_andi_i64(s, ret, arg, (1ull << len) - 1);
tcg_gen_shli_i64(s, ret, ret, ofs);
}
}
void tcg_gen_extract_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len)
{

6
qemu/tcg/tcg-op.h
View file

@ -300,6 +300,8 @@ void tcg_gen_rotr_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
void tcg_gen_rotri_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
unsigned int ofs, unsigned int len);
void tcg_gen_deposit_z_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_extract_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_sextract_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg,
@ -473,6 +475,8 @@ void tcg_gen_rotr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
void tcg_gen_rotri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
void tcg_gen_deposit_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
unsigned int ofs, unsigned int len);
void tcg_gen_deposit_z_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_extract_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_sextract_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg,
@ -961,6 +965,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
#define tcg_gen_deposit_tl tcg_gen_deposit_i64
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
#define tcg_gen_extract_tl tcg_gen_extract_i64
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
#define tcg_const_tl tcg_const_i64
@ -1051,6 +1056,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
#define tcg_gen_deposit_tl tcg_gen_deposit_i32
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
#define tcg_gen_extract_tl tcg_gen_extract_i32
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
#define tcg_const_tl tcg_const_i32

2
qemu/x86_64.h
View file

@ -3011,6 +3011,8 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_x86_64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_x86_64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_x86_64
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_x86_64
#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_x86_64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_x86_64
#define tcg_gen_div_i32 tcg_gen_div_i32_x86_64
#define tcg_gen_div_i64 tcg_gen_div_i64_x86_64