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target/arm: Simplify op_smlawx for SMLAW*

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By shifting the 16-bit input left by 16, we can align the desired
portion of the 48-bit product and use tcg_gen_muls2_i32.

Backports commit 485b607d4f393e0de92c922806a68aef22340c98 from qemu
This commit is contained in:
Richard Henderson 2019-11-19 14:13:50 -05:00 committed by Lioncash
parent 201be7b8b1
commit a011318794
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 8 deletions
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16
qemu/target/arm/translate.c
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@ -8464,7 +8464,6 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 t0, t1; TCGv_i32 t0, t1;
TCGv_i64 t64;
if (!ENABLE_ARCH_5TE) { if (!ENABLE_ARCH_5TE) {
return false; return false;
@ -8472,16 +8471,17 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt)
t0 = load_reg(s, a->rn); t0 = load_reg(s, a->rn);
t1 = load_reg(s, a->rm); t1 = load_reg(s, a->rm);
/*
* Since the nominal result is product<47:16>, shift the 16-bit
* input up by 16 bits, so that the result is at product<63:32>.
*/
if (mt) { if (mt) {
tcg_gen_sari_i32(tcg_ctx, t1, t1, 16); tcg_gen_andi_i32(tcg_ctx, t1, t1, 0xffff0000);
} else { } else {
gen_sxth(t1); tcg_gen_shli_i32(tcg_ctx, t1, t1, 16);
} }
t64 = gen_muls_i64_i32(s, t0, t1); tcg_gen_muls2_i32(tcg_ctx, t0, t1, t0, t1);
tcg_gen_shri_i64(tcg_ctx, t64, t64, 16); tcg_temp_free_i32(tcg_ctx, t0);
t1 = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, t1, t64);
tcg_temp_free_i64(tcg_ctx, t64);
if (add) { if (add) {
t0 = load_reg(s, a->ra); t0 = load_reg(s, a->ra);
gen_helper_add_setq(tcg_ctx, t1, tcg_ctx->cpu_env, t1, t0); gen_helper_add_setq(tcg_ctx, t1, tcg_ctx->cpu_env, t1, t0);