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arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16

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Backports commit 2deb992b767d28035fac3b374c7730494ff0b43d from qemu

Also backports the fp16 changes introduced in commit f566c0474a9b9bbd9ed248607e4007e24d3358c0
This commit is contained in:
Alex Bennée 2018-03-08 15:36:50 -05:00 committed by Lioncash
parent ba8df54753
commit a02b9b81a9
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GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 67 additions and 0 deletions
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2
qemu/aarch64.h
View file

@ -3731,7 +3731,9 @@
#define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64
#define helper_advsimd_minh helper_advsimd_minh_aarch64
#define helper_advsimd_minnumh helper_advsimd_minnumh_aarch64
#define helper_advsimd_muladdh helper_advsimd_muladdh_aarch64
#define helper_advsimd_mulh helper_advsimd_mulh_aarch64
#define helper_advsimd_mulxh helper_advsimd_mulxh_aarch64
#define helper_advsimd_subh helper_advsimd_subh_aarch64
#define helper_crc32_64 helper_crc32_64_aarch64
#define helper_crc32c_64 helper_crc32c_64_aarch64

2
qemu/aarch64eb.h
View file

@ -3731,7 +3731,9 @@
#define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64eb
#define helper_advsimd_minh helper_advsimd_minh_aarch64eb
#define helper_advsimd_minnumh helper_advsimd_minnumh_aarch64eb
#define helper_advsimd_muladdh helper_advsimd_muladdh_aarch64eb
#define helper_advsimd_mulh helper_advsimd_mulh_aarch64eb
#define helper_advsimd_mulxh helper_advsimd_mulxh_aarch64eb
#define helper_advsimd_subh helper_advsimd_subh_aarch64eb
#define helper_crc32_64 helper_crc32_64_aarch64eb
#define helper_crc32c_64 helper_crc32c_64_aarch64eb

2
qemu/header_gen.py
View file

@ -3751,7 +3751,9 @@ aarch64_symbols = (
'helper_advsimd_maxnumh',
'helper_advsimd_minh',
'helper_advsimd_minnumh',
'helper_advsimd_muladdh',
'helper_advsimd_mulh',
'helper_advsimd_mulxh',
'helper_advsimd_subh',
'helper_crc32_64',
'helper_crc32c_64',

20
qemu/include/fpu/softfloat.h
View file

@ -271,6 +271,26 @@ static inline int float16_is_any_nan(float16 a)
return ((float16_val(a) & ~0x8000) > 0x7c00);
}
static inline int float16_is_neg(float16 a)
{
return float16_val(a) >> 15;
}
static inline int float16_is_infinity(float16 a)
{
return (float16_val(a) & 0x7fff) == 0x7c00;
}
static inline int float16_is_zero(float16 a)
{
return (float16_val(a) & 0x7fff) == 0;
}
static inline int float16_is_zero_or_denormal(float16 a)
{
return (float16_val(a) & 0x7c00) == 0;
}
static inline float16 float16_abs(float16 a)
{
/* Note that abs does *not* handle NaN specially, nor does

24
qemu/target/arm/helper-a64.c
View file

@ -641,6 +641,30 @@ ADVSIMD_HALFOP(max)
ADVSIMD_HALFOP(minnum)
ADVSIMD_HALFOP(maxnum)
/* Data processing - scalar floating-point and advanced SIMD */
float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
{
float_status *fpst = fpstp;
a = float16_squash_input_denormal(a, fpst);
b = float16_squash_input_denormal(b, fpst);
if ((float16_is_zero(a) && float16_is_infinity(b)) ||
(float16_is_infinity(a) && float16_is_zero(b))) {
/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
return make_float16((1U << 14) |
((float16_val(a) ^ float16_val(b)) & (1U << 15)));
}
return float16_mul(a, b, fpst);
}
/* fused multiply-accumulate */
float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
{
float_status *fpst = fpstp;
return float16_muladd(a, b, c, 0, fpst);
}
/*
* Floating point comparisons produce an integer result. Softfloat
* routines return float_relation types which we convert to the 0/-1

2
qemu/target/arm/helper-a64.h
View file

@ -57,3 +57,5 @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)

15
qemu/target/arm/translate-a64.c
View file

@ -10438,9 +10438,17 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
case 0x0: /* FMAXNM */
gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1: /* FMLA */
read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
gen_helper_advsimd_muladdh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, tcg_res,
fpst);
break;
case 0x2: /* FADD */
gen_helper_advsimd_addh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x3: /* FMULX */
gen_helper_advsimd_mulxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x4: /* FCMEQ */
gen_helper_advsimd_ceq_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
@ -10450,6 +10458,13 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
case 0x8: /* FMINNM */
gen_helper_advsimd_minnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x9: /* FMLS */
/* As usual for ARM, separate negation for fused multiply-add */
tcg_gen_xori_i32(tcg_ctx, tcg_op1, tcg_op1, 0x8000);
read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
gen_helper_advsimd_muladdh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, tcg_res,
fpst);
break;
case 0xa: /* FSUB */
gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;