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target/mips: Add CP0 PWCtl register

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Add PWCtl register (CP0 Register 5, Select 6).

The PWCtl register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

PWEn (31) - Hardware Page Table walker enable
PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only)
XK (28) - If 1, walker handles xkseg (MIPS64 only)
XS (27) - If 1, walker handles xsseg (MIPS64 only)
XU (26) - If 1, walker handles xuseg (MIPS64 only)
DPH (7) - Dual Page format of Huge Page support
HugePg (6) - Huge Page PTE supported in Directory levels
PSn (5..0) - Bit position of PTEvld in Huge Page PTE

Backports commit 103be64c26c166f12b3e1308edadef3443723ff1 from qemu
This commit is contained in:
Yongbok Kim 2018-10-23 14:20:55 -04:00 committed by Lioncash
parent a5194f6dfc
commit a35a59bda6
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
9 changed files with 47 additions and 0 deletions
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1
qemu/header_gen.py
View file

@ -4934,6 +4934,7 @@ mips_symbols = (
'helper_mtc0_pagegrain',
'helper_mtc0_pagemask',
'helper_mtc0_performance0',
'helper_mtc0_pwctl',
'helper_mtc0_pwfield',
'helper_mtc0_pwsize',
'helper_mtc0_segctl0',

1
qemu/mips.h
View file

@ -3908,6 +3908,7 @@
#define helper_mtc0_pagegrain helper_mtc0_pagegrain_mips
#define helper_mtc0_pagemask helper_mtc0_pagemask_mips
#define helper_mtc0_performance0 helper_mtc0_performance0_mips
#define helper_mtc0_pwctl helper_mtc0_pwctl_mips
#define helper_mtc0_pwfield helper_mtc0_pwfield_mips
#define helper_mtc0_pwsize helper_mtc0_pwsize_mips
#define helper_mtc0_segctl0 helper_mtc0_segctl0_mips

1
qemu/mips64.h
View file

@ -3908,6 +3908,7 @@
#define helper_mtc0_pagegrain helper_mtc0_pagegrain_mips64
#define helper_mtc0_pagemask helper_mtc0_pagemask_mips64
#define helper_mtc0_performance0 helper_mtc0_performance0_mips64
#define helper_mtc0_pwctl helper_mtc0_pwctl_mips64
#define helper_mtc0_pwfield helper_mtc0_pwfield_mips64
#define helper_mtc0_pwsize helper_mtc0_pwsize_mips64
#define helper_mtc0_segctl0 helper_mtc0_segctl0_mips64

1
qemu/mips64el.h
View file

@ -3908,6 +3908,7 @@
#define helper_mtc0_pagegrain helper_mtc0_pagegrain_mips64el
#define helper_mtc0_pagemask helper_mtc0_pagemask_mips64el
#define helper_mtc0_performance0 helper_mtc0_performance0_mips64el
#define helper_mtc0_pwctl helper_mtc0_pwctl_mips64el
#define helper_mtc0_pwfield helper_mtc0_pwfield_mips64el
#define helper_mtc0_pwsize helper_mtc0_pwsize_mips64el
#define helper_mtc0_segctl0 helper_mtc0_segctl0_mips64el

1
qemu/mipsel.h
View file

@ -3908,6 +3908,7 @@
#define helper_mtc0_pagegrain helper_mtc0_pagegrain_mipsel
#define helper_mtc0_pagemask helper_mtc0_pagemask_mipsel
#define helper_mtc0_performance0 helper_mtc0_performance0_mipsel
#define helper_mtc0_pwctl helper_mtc0_pwctl_mipsel
#define helper_mtc0_pwfield helper_mtc0_pwfield_mipsel
#define helper_mtc0_pwsize helper_mtc0_pwsize_mipsel
#define helper_mtc0_segctl0 helper_mtc0_segctl0_mipsel

11
qemu/target/mips/cpu.h
View file

@ -447,6 +447,17 @@ struct CPUMIPSState {
* CP0 Register 6
*/
int32_t CP0_Wired;
int32_t CP0_PWCtl;
#define CP0PC_PWEN 31
#if defined(TARGET_MIPS64)
#define CP0PC_PWDIREXT 30
#define CP0PC_XK 28
#define CP0PC_XS 27
#define CP0PC_XU 26
#endif
#define CP0PC_DPH 7
#define CP0PC_HUGEPG 6
#define CP0PC_PSN 0 /* 5..0 */
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
#define CP0SRSC0_M 31

1
qemu/target/mips/helper.h
View file

@ -129,6 +129,7 @@ DEF_HELPER_2(mtc0_srsconf2, void, env, tl)
DEF_HELPER_2(mtc0_srsconf3, void, env, tl)
DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
DEF_HELPER_2(mtc0_count, void, env, tl)
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
DEF_HELPER_2(mttc0_entryhi, void, env, tl)

10
qemu/target/mips/op_helper.c
View file

@ -1517,6 +1517,16 @@ void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
}
}
void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
{
#if defined(TARGET_MIPS64)
/* PWEn = 0. Hardware page table walking is not implemented. */
env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
#else
env->CP0_PWCtl = (arg1 & 0x800000FF);
#endif
}
void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;

20
qemu/target/mips/translate.c
View file

@ -6240,6 +6240,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
case 6:
check_pw(ctx);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWCtl));
rn = "PWCtl";
break;
default:
goto cp0_unimplemented;
}
@ -6952,6 +6957,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_srsconf4(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "SRSConf4";
break;
case 6:
check_pw(ctx);
gen_helper_mtc0_pwctl(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "PWCtl";
break;
default:
goto cp0_unimplemented;
}
@ -7674,6 +7684,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
case 6:
check_pw(ctx);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWCtl));
rn = "PWCtl";
break;
default:
goto cp0_unimplemented;
}
@ -8368,6 +8383,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_srsconf4(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "SRSConf4";
break;
case 6:
check_pw(ctx);
gen_helper_mtc0_pwctl(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "PWCtl";
break;
default:
goto cp0_unimplemented;
}