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target-mips: enable 10-bit ASIDs in I6400 CPU
Backports commit cdc46fab07a122dfcc8a1054510a68d936ae3440 from qemu
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@ -827,7 +827,7 @@ static const mips_def_t mips_defs[] =
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(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
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(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
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MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
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(0xfc << CP0C4_KScrExist),
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(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
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MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
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(1 << CP0C5_LLB) | (1 << CP0C5_MRP),
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(1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
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