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target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd

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Backports 3607440c4df6498585a570cfc1041e4972b41b56
This commit is contained in:
Richard Henderson 2021-02-26 14:51:15 -05:00 committed by Lioncash
parent 732674b868
commit aa97b6b755
6 changed files with 96 additions and 5 deletions
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6
qemu/aarch64.h
View file

@ -3582,6 +3582,12 @@
#define helper_frecpx_f32 helper_frecpx_f32_aarch64
#define helper_frecpx_f64 helper_frecpx_f64_aarch64
#define helper_fjcvtzs helper_fjcvtzs_aarch64
#define helper_gvec_mla_idx_d helper_gvec_mla_idx_d_aarch64
#define helper_gvec_mla_idx_h helper_gvec_mla_idx_h_aarch64
#define helper_gvec_mla_idx_s helper_gvec_mla_idx_s_aarch64
#define helper_gvec_mls_idx_d helper_gvec_mls_idx_d_aarch64
#define helper_gvec_mls_idx_h helper_gvec_mls_idx_h_aarch64
#define helper_gvec_mls_idx_s helper_gvec_mls_idx_s_aarch64
#define helper_gvec_mul_idx_d helper_gvec_mul_idx_d_aarch64
#define helper_gvec_mul_idx_h helper_gvec_mul_idx_h_aarch64
#define helper_gvec_mul_idx_s helper_gvec_mul_idx_s_aarch64

6
qemu/aarch64eb.h
View file

@ -3582,6 +3582,12 @@
#define helper_frecpx_f32 helper_frecpx_f32_aarch64eb
#define helper_frecpx_f64 helper_frecpx_f64_aarch64eb
#define helper_fjcvtzs helper_fjcvtzs_aarch64eb
#define helper_gvec_mla_idx_d helper_gvec_mla_idx_d_aarch64eb
#define helper_gvec_mla_idx_h helper_gvec_mla_idx_h_aarch64eb
#define helper_gvec_mla_idx_s helper_gvec_mla_idx_s_aarch64eb
#define helper_gvec_mls_idx_d helper_gvec_mls_idx_d_aarch64eb
#define helper_gvec_mls_idx_h helper_gvec_mls_idx_h_aarch64eb
#define helper_gvec_mls_idx_s helper_gvec_mls_idx_s_aarch64eb
#define helper_gvec_mul_idx_d helper_gvec_mul_idx_d_aarch64eb
#define helper_gvec_mul_idx_h helper_gvec_mul_idx_h_aarch64eb
#define helper_gvec_mul_idx_s helper_gvec_mul_idx_s_aarch64eb

6
qemu/header_gen.py
View file

@ -3722,6 +3722,12 @@ aarch64_symbols = (
'helper_frecpx_f32',
'helper_frecpx_f64',
'helper_fjcvtzs',
'helper_gvec_mla_idx_d',
'helper_gvec_mla_idx_h',
'helper_gvec_mla_idx_s',
'helper_gvec_mls_idx_d',
'helper_gvec_mls_idx_h',
'helper_gvec_mls_idx_s',
'helper_gvec_mul_idx_d',
'helper_gvec_mul_idx_h',
'helper_gvec_mul_idx_s',

14
qemu/target/arm/helper.h
View file

@ -760,6 +760,20 @@ DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
#ifdef TARGET_ARM
#define helper_clz helper_clz_arm
#define gen_helper_clz gen_helper_clz_arm

34
qemu/target/arm/translate-a64.c
View file

@ -13814,6 +13814,40 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
return;
}
break;
case 0x10: /* MLA */
if (!is_long && !is_scalar) {
static gen_helper_gvec_4 * const fns[3] = {
gen_helper_gvec_mla_idx_h,
gen_helper_gvec_mla_idx_s,
gen_helper_gvec_mla_idx_d,
};
tcg_gen_gvec_4_ool(tcg_ctx, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s),
index, fns[size - 1]);
return;
}
break;
case 0x14: /* MLS */
if (!is_long && !is_scalar) {
static gen_helper_gvec_4 * const fns[3] = {
gen_helper_gvec_mls_idx_h,
gen_helper_gvec_mls_idx_s,
gen_helper_gvec_mls_idx_d,
};
tcg_gen_gvec_4_ool(tcg_ctx, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s),
index, fns[size - 1]);
return;
}
break;
}
if (size == 3) {

35
qemu/target/arm/vec_helper.c
View file

@ -732,7 +732,32 @@ DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
#undef DO_MUL_IDX
#define DO_MUL_IDX(NAME, TYPE, H) \
#define DO_MLA_IDX(NAME, TYPE, OP, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
{ \
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
intptr_t idx = simd_data(desc); \
TYPE *d = vd, *n = vn, *m = vm, *a = va; \
for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
TYPE mm = m[H(i + idx)]; \
for (j = 0; j < segment; j++) { \
d[i + j] = a[i + j] OP n[i + j] * mm; \
} \
} \
clear_tail(d, oprsz, simd_maxsz(desc)); \
}
DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2)
DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4)
DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, )
DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2)
DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4)
DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, )
#undef DO_MLA_IDX
#define DO_FMUL_IDX(NAME, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
{ \
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
@ -747,11 +772,11 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
clear_tail(d, oprsz, simd_maxsz(desc)); \
}
DO_MUL_IDX(gvec_fmul_idx_h, float16, H2)
DO_MUL_IDX(gvec_fmul_idx_s, float32, H4)
DO_MUL_IDX(gvec_fmul_idx_d, float64, )
DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2)
DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4)
DO_FMUL_IDX(gvec_fmul_idx_d, float64, )
#undef DO_MUL_IDX
#undef DO_FMUL_IDX
#define DO_FMLA_IDX(NAME, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \