mirror of
https://github.com/yuzu-emu/unicorn.git
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target/arm: Decode aa64 armv8.3 fcmla
Backports commit d17b7cdcf4ea3e858ceee8b86fc8544bb71561e6 from qemu Also remember to commit vec_helper.
This commit is contained in:
Richard Henderson
Lioncash
parent
4b39a36416
commit
abd86b2287
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_aarch64
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#define helper_gvec_fcadds helper_gvec_fcadds_aarch64
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#define helper_gvec_fcaddd helper_gvec_fcaddd_aarch64
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#define helper_gvec_fcmlad helper_gvec_fcmlad_aarch64
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#define helper_gvec_fcmlah helper_gvec_fcmlah_aarch64
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_aarch64
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#define helper_gvec_fcmlas helper_gvec_fcmlas_aarch64
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_aarch64
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#define helper_gvec_le8 helper_gvec_le8_aarch64
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#define helper_gvec_le16 helper_gvec_le16_aarch64
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#define helper_gvec_le32 helper_gvec_le32_aarch64
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_aarch64eb
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#define helper_gvec_fcadds helper_gvec_fcadds_aarch64eb
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#define helper_gvec_fcaddd helper_gvec_fcaddd_aarch64eb
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#define helper_gvec_fcmlad helper_gvec_fcmlad_aarch64eb
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#define helper_gvec_fcmlah helper_gvec_fcmlah_aarch64eb
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_aarch64eb
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#define helper_gvec_fcmlas helper_gvec_fcmlas_aarch64eb
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_aarch64eb
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#define helper_gvec_le8 helper_gvec_le8_aarch64eb
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#define helper_gvec_le16 helper_gvec_le16_aarch64eb
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#define helper_gvec_le32 helper_gvec_le32_aarch64eb
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_arm
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#define helper_gvec_fcadds helper_gvec_fcadds_arm
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#define helper_gvec_fcaddd helper_gvec_fcaddd_arm
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#define helper_gvec_fcmlad helper_gvec_fcmlad_arm
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#define helper_gvec_fcmlah helper_gvec_fcmlah_arm
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_arm
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#define helper_gvec_fcmlas helper_gvec_fcmlas_arm
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_arm
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#define helper_gvec_le8 helper_gvec_le8_arm
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#define helper_gvec_le16 helper_gvec_le16_arm
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#define helper_gvec_le32 helper_gvec_le32_arm
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_armeb
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#define helper_gvec_fcadds helper_gvec_fcadds_armeb
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#define helper_gvec_fcaddd helper_gvec_fcaddd_armeb
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#define helper_gvec_fcmlad helper_gvec_fcmlad_armeb
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#define helper_gvec_fcmlah helper_gvec_fcmlah_armeb
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_armeb
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#define helper_gvec_fcmlas helper_gvec_fcmlas_armeb
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_armeb
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#define helper_gvec_le8 helper_gvec_le8_armeb
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#define helper_gvec_le16 helper_gvec_le16_armeb
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#define helper_gvec_le32 helper_gvec_le32_armeb
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@ -1002,6 +1002,11 @@ symbols = (
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'helper_gvec_fcaddh',
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'helper_gvec_fcadds',
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'helper_gvec_fcaddd',
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'helper_gvec_fcmlad',
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'helper_gvec_fcmlah',
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'helper_gvec_fcmlah_idx',
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'helper_gvec_fcmlas',
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'helper_gvec_fcmlas_idx',
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'helper_gvec_le8',
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'helper_gvec_le16',
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'helper_gvec_le32',
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_m68k
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#define helper_gvec_fcadds helper_gvec_fcadds_m68k
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#define helper_gvec_fcaddd helper_gvec_fcaddd_m68k
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#define helper_gvec_fcmlad helper_gvec_fcmlad_m68k
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#define helper_gvec_fcmlah helper_gvec_fcmlah_m68k
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_m68k
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#define helper_gvec_fcmlas helper_gvec_fcmlas_m68k
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_m68k
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#define helper_gvec_le8 helper_gvec_le8_m68k
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#define helper_gvec_le16 helper_gvec_le16_m68k
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#define helper_gvec_le32 helper_gvec_le32_m68k
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_mips
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#define helper_gvec_fcadds helper_gvec_fcadds_mips
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#define helper_gvec_fcaddd helper_gvec_fcaddd_mips
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#define helper_gvec_fcmlad helper_gvec_fcmlad_mips
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#define helper_gvec_fcmlah helper_gvec_fcmlah_mips
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_mips
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#define helper_gvec_fcmlas helper_gvec_fcmlas_mips
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_mips
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#define helper_gvec_le8 helper_gvec_le8_mips
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#define helper_gvec_le16 helper_gvec_le16_mips
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#define helper_gvec_le32 helper_gvec_le32_mips
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_mips64
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#define helper_gvec_fcadds helper_gvec_fcadds_mips64
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#define helper_gvec_fcaddd helper_gvec_fcaddd_mips64
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#define helper_gvec_fcmlad helper_gvec_fcmlad_mips64
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#define helper_gvec_fcmlah helper_gvec_fcmlah_mips64
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_mips64
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#define helper_gvec_fcmlas helper_gvec_fcmlas_mips64
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_mips64
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#define helper_gvec_le8 helper_gvec_le8_mips64
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#define helper_gvec_le16 helper_gvec_le16_mips64
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#define helper_gvec_le32 helper_gvec_le32_mips64
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_mips64el
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#define helper_gvec_fcadds helper_gvec_fcadds_mips64el
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#define helper_gvec_fcaddd helper_gvec_fcaddd_mips64el
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#define helper_gvec_fcmlad helper_gvec_fcmlad_mips64el
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#define helper_gvec_fcmlah helper_gvec_fcmlah_mips64el
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_mips64el
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#define helper_gvec_fcmlas helper_gvec_fcmlas_mips64el
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_mips64el
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#define helper_gvec_le8 helper_gvec_le8_mips64el
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#define helper_gvec_le16 helper_gvec_le16_mips64el
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#define helper_gvec_le32 helper_gvec_le32_mips64el
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_mipsel
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#define helper_gvec_fcadds helper_gvec_fcadds_mipsel
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#define helper_gvec_fcaddd helper_gvec_fcaddd_mipsel
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#define helper_gvec_fcmlad helper_gvec_fcmlad_mipsel
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#define helper_gvec_fcmlah helper_gvec_fcmlah_mipsel
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_mipsel
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#define helper_gvec_fcmlas helper_gvec_fcmlas_mipsel
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_mipsel
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#define helper_gvec_le8 helper_gvec_le8_mipsel
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#define helper_gvec_le16 helper_gvec_le16_mipsel
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#define helper_gvec_le32 helper_gvec_le32_mipsel
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_powerpc
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#define helper_gvec_fcadds helper_gvec_fcadds_powerpc
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#define helper_gvec_fcaddd helper_gvec_fcaddd_powerpc
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#define helper_gvec_fcmlad helper_gvec_fcmlad_powerpc
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#define helper_gvec_fcmlah helper_gvec_fcmlah_powerpc
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_powerpc
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#define helper_gvec_fcmlas helper_gvec_fcmlas_powerpc
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_powerpc
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#define helper_gvec_le8 helper_gvec_le8_powerpc
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#define helper_gvec_le16 helper_gvec_le16_powerpc
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#define helper_gvec_le32 helper_gvec_le32_powerpc
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_sparc
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#define helper_gvec_fcadds helper_gvec_fcadds_sparc
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#define helper_gvec_fcaddd helper_gvec_fcaddd_sparc
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#define helper_gvec_fcmlad helper_gvec_fcmlad_sparc
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#define helper_gvec_fcmlah helper_gvec_fcmlah_sparc
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_sparc
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#define helper_gvec_fcmlas helper_gvec_fcmlas_sparc
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_sparc
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#define helper_gvec_le8 helper_gvec_le8_sparc
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#define helper_gvec_le16 helper_gvec_le16_sparc
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#define helper_gvec_le32 helper_gvec_le32_sparc
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@ -996,6 +996,11 @@
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#define helper_gvec_fcaddh helper_gvec_fcaddh_sparc64
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#define helper_gvec_fcadds helper_gvec_fcadds_sparc64
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#define helper_gvec_fcaddd helper_gvec_fcaddd_sparc64
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#define helper_gvec_fcmlad helper_gvec_fcmlad_sparc64
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#define helper_gvec_fcmlah helper_gvec_fcmlah_sparc64
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#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_sparc64
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#define helper_gvec_fcmlas helper_gvec_fcmlas_sparc64
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#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_sparc64
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#define helper_gvec_le8 helper_gvec_le8_sparc64
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#define helper_gvec_le16 helper_gvec_le16_sparc64
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#define helper_gvec_le32 helper_gvec_le32_sparc64
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@ -587,6 +587,17 @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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#ifdef TARGET_ARM
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#define helper_clz helper_clz_arm
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#define gen_helper_clz gen_helper_clz_arm
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@ -10995,6 +10995,10 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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}
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feature = ARM_FEATURE_V8_RDM;
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break;
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case 0x8: /* FCMLA, #0 */
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case 0x9: /* FCMLA, #90 */
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case 0xa: /* FCMLA, #180 */
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case 0xb: /* FCMLA, #270 */
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case 0xc: /* FCADD, #90 */
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case 0xe: /* FCADD, #270 */
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if (size == 0
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@ -11065,6 +11069,29 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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}
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return;
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case 0x8: /* FCMLA, #0 */
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case 0x9: /* FCMLA, #90 */
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case 0xa: /* FCMLA, #180 */
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case 0xb: /* FCMLA, #270 */
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rot = extract32(opcode, 0, 2);
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switch (size) {
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case 1:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot,
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gen_helper_gvec_fcmlah);
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break;
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case 2:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
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gen_helper_gvec_fcmlas);
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break;
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case 3:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
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gen_helper_gvec_fcmlad);
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break;
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default:
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g_assert_not_reached();
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}
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return;
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default:
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g_assert_not_reached();
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}
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@ -12152,7 +12179,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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bool is_long = false;
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bool is_fp = false;
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int is_fp = 0;
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bool is_fp16 = false;
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int index;
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TCGv_ptr fpst;
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@ -12190,7 +12217,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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case 0x05: /* FMLS */
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case 0x09: /* FMUL */
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case 0x19: /* FMULX */
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is_fp = true;
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is_fp = 1;
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break;
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case 0x1d: /* SQRDMLAH */
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case 0x1f: /* SQRDMLSH */
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@ -12199,20 +12226,28 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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return;
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}
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break;
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case 0x11: /* FCMLA #0 */
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case 0x13: /* FCMLA #90 */
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case 0x15: /* FCMLA #180 */
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case 0x17: /* FCMLA #270 */
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if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) {
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unallocated_encoding(s);
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return;
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}
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is_fp = 2;
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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if (is_fp) {
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switch (is_fp) {
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case 1: /* normal fp */
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/* convert insn encoded size to TCGMemOp size */
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switch (size) {
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case 0: /* half-precision */
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if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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unallocated_encoding(s);
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return;
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}
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size = MO_16;
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is_fp16 = true;
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break;
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case MO_32: /* single precision */
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case MO_64: /* double precision */
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@ -12221,13 +12256,39 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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return;
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}
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} else {
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break;
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case 2: /* complex fp */
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/* Each indexable element is a complex pair. */
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size <<= 1;
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switch (size) {
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case MO_32:
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if (h && !is_q) {
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unallocated_encoding(s);
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return;
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}
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is_fp16 = true;
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break;
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case MO_64:
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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break;
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default: /* integer */
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switch (size) {
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case MO_8:
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case MO_64:
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unallocated_encoding(s);
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return;
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}
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break;
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}
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if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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unallocated_encoding(s);
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return;
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}
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/* Given TCGMemOp size, adjust register and indexing. */
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@ -12261,6 +12322,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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fpst = NULL;
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}
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switch (16 * u + opcode) {
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case 0x11: /* FCMLA #0 */
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case 0x13: /* FCMLA #90 */
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case 0x15: /* FCMLA #180 */
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case 0x17: /* FCMLA #270 */
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tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rn),
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vec_reg_offset(s, rm, index, size), fpst,
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is_q ? 16 : 8, vec_full_reg_size(s),
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extract32(insn, 13, 2), /* rot */
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size == MO_64
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? gen_helper_gvec_fcmlas_idx
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: gen_helper_gvec_fcmlah_idx);
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tcg_temp_free_ptr(tcg_ctx, fpst);
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return;
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}
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if (size == 3) {
|
||||
TCGv_i64 tcg_idx = tcg_temp_new_i64(tcg_ctx);
|
||||
int pass;
|
||||
|
|
|
|||
428
qemu/target/arm/vec_helper.c
Normal file
428
qemu/target/arm/vec_helper.c
Normal file
|
|
@ -0,0 +1,428 @@
|
|||
/*
|
||||
* ARM AdvSIMD / SVE Vector Operations
|
||||
*
|
||||
* Copyright (c) 2018 Linaro
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/helper-proto.h"
|
||||
#include "tcg/tcg-gvec-desc.h"
|
||||
#include "fpu/softfloat.h"
|
||||
|
||||
/* Note that vector data is stored in host-endian 64-bit chunks,
|
||||
so addressing units smaller than that needs a host-endian fixup. */
|
||||
#ifdef HOST_WORDS_BIGENDIAN
|
||||
#define H1(x) ((x) ^ 7)
|
||||
#define H2(x) ((x) ^ 3)
|
||||
#define H4(x) ((x) ^ 1)
|
||||
#else
|
||||
#define H1(x) (x)
|
||||
#define H2(x) (x)
|
||||
#define H4(x) (x)
|
||||
#endif
|
||||
|
||||
#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
|
||||
|
||||
static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
|
||||
{
|
||||
uint64_t *d = vd + opr_sz;
|
||||
uintptr_t i;
|
||||
|
||||
for (i = opr_sz; i < max_sz; i += 8) {
|
||||
*d++ = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
|
||||
static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1,
|
||||
int16_t src2, int16_t src3)
|
||||
{
|
||||
/* Simplify:
|
||||
* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
|
||||
* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
|
||||
*/
|
||||
int32_t ret = (int32_t)src1 * src2;
|
||||
ret = ((int32_t)src3 << 15) + ret + (1 << 14);
|
||||
ret >>= 15;
|
||||
if (ret != (int16_t)ret) {
|
||||
SET_QC();
|
||||
ret = (ret < 0 ? -0x8000 : 0x7fff);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
|
||||
uint32_t src2, uint32_t src3)
|
||||
{
|
||||
uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3);
|
||||
uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
|
||||
return deposit32(e1, 16, 16, e2);
|
||||
}
|
||||
|
||||
void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
|
||||
void *ve, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
int16_t *d = vd;
|
||||
int16_t *n = vn;
|
||||
int16_t *m = vm;
|
||||
CPUARMState *env = ve;
|
||||
uintptr_t i;
|
||||
|
||||
for (i = 0; i < opr_sz / 2; ++i) {
|
||||
d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
|
||||
static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1,
|
||||
int16_t src2, int16_t src3)
|
||||
{
|
||||
/* Similarly, using subtraction:
|
||||
* = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
|
||||
* = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
|
||||
*/
|
||||
int32_t ret = (int32_t)src1 * src2;
|
||||
ret = ((int32_t)src3 << 15) - ret + (1 << 14);
|
||||
ret >>= 15;
|
||||
if (ret != (int16_t)ret) {
|
||||
SET_QC();
|
||||
ret = (ret < 0 ? -0x8000 : 0x7fff);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
|
||||
uint32_t src2, uint32_t src3)
|
||||
{
|
||||
uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3);
|
||||
uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
|
||||
return deposit32(e1, 16, 16, e2);
|
||||
}
|
||||
|
||||
void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
|
||||
void *ve, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
int16_t *d = vd;
|
||||
int16_t *n = vn;
|
||||
int16_t *m = vm;
|
||||
CPUARMState *env = ve;
|
||||
uintptr_t i;
|
||||
|
||||
for (i = 0; i < opr_sz / 2; ++i) {
|
||||
d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
|
||||
uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
|
||||
int32_t src2, int32_t src3)
|
||||
{
|
||||
/* Simplify similarly to int_qrdmlah_s16 above. */
|
||||
int64_t ret = (int64_t)src1 * src2;
|
||||
ret = ((int64_t)src3 << 31) + ret + (1 << 30);
|
||||
ret >>= 31;
|
||||
if (ret != (int32_t)ret) {
|
||||
SET_QC();
|
||||
ret = (ret < 0 ? INT32_MIN : INT32_MAX);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
|
||||
void *ve, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
int32_t *d = vd;
|
||||
int32_t *n = vn;
|
||||
int32_t *m = vm;
|
||||
CPUARMState *env = ve;
|
||||
uintptr_t i;
|
||||
|
||||
for (i = 0; i < opr_sz / 4; ++i) {
|
||||
d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
|
||||
uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
|
||||
int32_t src2, int32_t src3)
|
||||
{
|
||||
/* Simplify similarly to int_qrdmlsh_s16 above. */
|
||||
int64_t ret = (int64_t)src1 * src2;
|
||||
ret = ((int64_t)src3 << 31) - ret + (1 << 30);
|
||||
ret >>= 31;
|
||||
if (ret != (int32_t)ret) {
|
||||
SET_QC();
|
||||
ret = (ret < 0 ? INT32_MIN : INT32_MAX);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
|
||||
void *ve, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
int32_t *d = vd;
|
||||
int32_t *n = vn;
|
||||
int32_t *m = vm;
|
||||
CPUARMState *env = ve;
|
||||
uintptr_t i;
|
||||
|
||||
for (i = 0; i < opr_sz / 4; ++i) {
|
||||
d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
|
||||
void *vfpst, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
float16 *d = vd;
|
||||
float16 *n = vn;
|
||||
float16 *m = vm;
|
||||
float_status *fpst = vfpst;
|
||||
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
|
||||
uint32_t neg_imag = neg_real ^ 1;
|
||||
uintptr_t i;
|
||||
|
||||
/* Shift boolean to the sign bit so we can xor to negate. */
|
||||
neg_real <<= 15;
|
||||
neg_imag <<= 15;
|
||||
|
||||
for (i = 0; i < opr_sz / 2; i += 2) {
|
||||
float16 e0 = n[H2(i)];
|
||||
float16 e1 = m[H2(i + 1)] ^ neg_imag;
|
||||
float16 e2 = n[H2(i + 1)];
|
||||
float16 e3 = m[H2(i)] ^ neg_real;
|
||||
|
||||
d[H2(i)] = float16_add(e0, e1, fpst);
|
||||
d[H2(i + 1)] = float16_add(e2, e3, fpst);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
|
||||
void *vfpst, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
float32 *d = vd;
|
||||
float32 *n = vn;
|
||||
float32 *m = vm;
|
||||
float_status *fpst = vfpst;
|
||||
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
|
||||
uint32_t neg_imag = neg_real ^ 1;
|
||||
uintptr_t i;
|
||||
|
||||
/* Shift boolean to the sign bit so we can xor to negate. */
|
||||
neg_real <<= 31;
|
||||
neg_imag <<= 31;
|
||||
|
||||
for (i = 0; i < opr_sz / 4; i += 2) {
|
||||
float32 e0 = n[H4(i)];
|
||||
float32 e1 = m[H4(i + 1)] ^ neg_imag;
|
||||
float32 e2 = n[H4(i + 1)];
|
||||
float32 e3 = m[H4(i)] ^ neg_real;
|
||||
|
||||
d[H4(i)] = float32_add(e0, e1, fpst);
|
||||
d[H4(i + 1)] = float32_add(e2, e3, fpst);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
|
||||
void *vfpst, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
float64 *d = vd;
|
||||
float64 *n = vn;
|
||||
float64 *m = vm;
|
||||
float_status *fpst = vfpst;
|
||||
uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
|
||||
uint64_t neg_imag = neg_real ^ 1;
|
||||
uintptr_t i;
|
||||
|
||||
/* Shift boolean to the sign bit so we can xor to negate. */
|
||||
neg_real <<= 63;
|
||||
neg_imag <<= 63;
|
||||
|
||||
for (i = 0; i < opr_sz / 8; i += 2) {
|
||||
float64 e0 = n[i];
|
||||
float64 e1 = m[i + 1] ^ neg_imag;
|
||||
float64 e2 = n[i + 1];
|
||||
float64 e3 = m[i] ^ neg_real;
|
||||
|
||||
d[i] = float64_add(e0, e1, fpst);
|
||||
d[i + 1] = float64_add(e2, e3, fpst);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
|
||||
void *vfpst, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
float16 *d = vd;
|
||||
float16 *n = vn;
|
||||
float16 *m = vm;
|
||||
float_status *fpst = vfpst;
|
||||
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
||||
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
||||
uint32_t neg_real = flip ^ neg_imag;
|
||||
uintptr_t i;
|
||||
|
||||
/* Shift boolean to the sign bit so we can xor to negate. */
|
||||
neg_real <<= 15;
|
||||
neg_imag <<= 15;
|
||||
|
||||
for (i = 0; i < opr_sz / 2; i += 2) {
|
||||
float16 e2 = n[H2(i + flip)];
|
||||
float16 e1 = m[H2(i + flip)] ^ neg_real;
|
||||
float16 e4 = e2;
|
||||
float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag;
|
||||
|
||||
d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
|
||||
d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm,
|
||||
void *vfpst, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
float16 *d = vd;
|
||||
float16 *n = vn;
|
||||
float16 *m = vm;
|
||||
float_status *fpst = vfpst;
|
||||
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
||||
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
||||
uint32_t neg_real = flip ^ neg_imag;
|
||||
uintptr_t i;
|
||||
float16 e1 = m[H2(flip)];
|
||||
float16 e3 = m[H2(1 - flip)];
|
||||
|
||||
/* Shift boolean to the sign bit so we can xor to negate. */
|
||||
neg_real <<= 15;
|
||||
neg_imag <<= 15;
|
||||
e1 ^= neg_real;
|
||||
e3 ^= neg_imag;
|
||||
|
||||
for (i = 0; i < opr_sz / 2; i += 2) {
|
||||
float16 e2 = n[H2(i + flip)];
|
||||
float16 e4 = e2;
|
||||
|
||||
d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
|
||||
d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm,
|
||||
void *vfpst, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
float32 *d = vd;
|
||||
float32 *n = vn;
|
||||
float32 *m = vm;
|
||||
float_status *fpst = vfpst;
|
||||
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
||||
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
||||
uint32_t neg_real = flip ^ neg_imag;
|
||||
uintptr_t i;
|
||||
|
||||
/* Shift boolean to the sign bit so we can xor to negate. */
|
||||
neg_real <<= 31;
|
||||
neg_imag <<= 31;
|
||||
|
||||
for (i = 0; i < opr_sz / 4; i += 2) {
|
||||
float32 e2 = n[H4(i + flip)];
|
||||
float32 e1 = m[H4(i + flip)] ^ neg_real;
|
||||
float32 e4 = e2;
|
||||
float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag;
|
||||
|
||||
d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
|
||||
d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm,
|
||||
void *vfpst, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
float32 *d = vd;
|
||||
float32 *n = vn;
|
||||
float32 *m = vm;
|
||||
float_status *fpst = vfpst;
|
||||
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
||||
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
||||
uint32_t neg_real = flip ^ neg_imag;
|
||||
uintptr_t i;
|
||||
float32 e1 = m[H4(flip)];
|
||||
float32 e3 = m[H4(1 - flip)];
|
||||
|
||||
/* Shift boolean to the sign bit so we can xor to negate. */
|
||||
neg_real <<= 31;
|
||||
neg_imag <<= 31;
|
||||
e1 ^= neg_real;
|
||||
e3 ^= neg_imag;
|
||||
|
||||
for (i = 0; i < opr_sz / 4; i += 2) {
|
||||
float32 e2 = n[H4(i + flip)];
|
||||
float32 e4 = e2;
|
||||
|
||||
d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
|
||||
d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm,
|
||||
void *vfpst, uint32_t desc)
|
||||
{
|
||||
uintptr_t opr_sz = simd_oprsz(desc);
|
||||
float64 *d = vd;
|
||||
float64 *n = vn;
|
||||
float64 *m = vm;
|
||||
float_status *fpst = vfpst;
|
||||
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
||||
uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
||||
uint64_t neg_real = flip ^ neg_imag;
|
||||
uintptr_t i;
|
||||
|
||||
/* Shift boolean to the sign bit so we can xor to negate. */
|
||||
neg_real <<= 63;
|
||||
neg_imag <<= 63;
|
||||
|
||||
for (i = 0; i < opr_sz / 8; i += 2) {
|
||||
float64 e2 = n[i + flip];
|
||||
float64 e1 = m[i + flip] ^ neg_real;
|
||||
float64 e4 = e2;
|
||||
float64 e3 = m[i + 1 - flip] ^ neg_imag;
|
||||
|
||||
d[i] = float64_muladd(e2, e1, d[i], 0, fpst);
|
||||
d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst);
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
|
@ -996,6 +996,11 @@
|
|||
#define helper_gvec_fcaddh helper_gvec_fcaddh_x86_64
|
||||
#define helper_gvec_fcadds helper_gvec_fcadds_x86_64
|
||||
#define helper_gvec_fcaddd helper_gvec_fcaddd_x86_64
|
||||
#define helper_gvec_fcmlad helper_gvec_fcmlad_x86_64
|
||||
#define helper_gvec_fcmlah helper_gvec_fcmlah_x86_64
|
||||
#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_x86_64
|
||||
#define helper_gvec_fcmlas helper_gvec_fcmlas_x86_64
|
||||
#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_x86_64
|
||||
#define helper_gvec_le8 helper_gvec_le8_x86_64
|
||||
#define helper_gvec_le16 helper_gvec_le16_x86_64
|
||||
#define helper_gvec_le32 helper_gvec_le32_x86_64
|
||||
|
|
|
|||
Loading…
Reference in a new issue