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target/arm: Revise decoding for disas_add_sub_imm

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The current Arm ARM has adjusted the official decode of
"Add/subtract (immediate)" so that the shift field is only bit 22,
and bit 23 is part of the op1 field of the parent category
"Data processing - immediate".

Backports commit 21a8b343eaae63f6984f9a200092b0ea167647f1 from qemu
This commit is contained in:
Richard Henderson 2021-02-25 14:38:43 -05:00 committed by Lioncash
parent 58f3dd2cc7
commit acd7e4cb18
1 changed files with 8 additions and 15 deletions
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23
qemu/target/arm/translate-a64.c
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@ -3949,15 +3949,15 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
/* /*
* Add/subtract (immediate) * Add/subtract (immediate)
* *
* 31 30 29 28 24 23 22 21 10 9 5 4 0 * 31 30 29 28 23 22 21 10 9 5 4 0
* +--+--+--+-----------+-----+-------------+-----+-----+ * +--+--+--+-------------+--+-------------+-----+-----+
* |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
* +--+--+--+-----------+-----+-------------+-----+-----+ * +--+--+--+-------------+--+-------------+-----+-----+
* *
* sf: 0 -> 32bit, 1 -> 64bit * sf: 0 -> 32bit, 1 -> 64bit
* op: 0 -> add , 1 -> sub * op: 0 -> add , 1 -> sub
* S: 1 -> set flags * S: 1 -> set flags
* shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 * sh: 1 -> LSL imm by 12
*/ */
static void disas_add_sub_imm(DisasContext *s, uint32_t insn) static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
{ {
@ -3965,7 +3965,7 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
int rd = extract32(insn, 0, 5); int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5); int rn = extract32(insn, 5, 5);
uint64_t imm = extract32(insn, 10, 12); uint64_t imm = extract32(insn, 10, 12);
int shift = extract32(insn, 22, 2); bool shift = extract32(insn, 22, 1);
bool setflags = extract32(insn, 29, 1); bool setflags = extract32(insn, 29, 1);
bool sub_op = extract32(insn, 30, 1); bool sub_op = extract32(insn, 30, 1);
bool is_64bit = extract32(insn, 31, 1); bool is_64bit = extract32(insn, 31, 1);
@ -3974,15 +3974,8 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
TCGv_i64 tcg_result; TCGv_i64 tcg_result;
switch (shift) { if (shift) {
case 0x0:
break;
case 0x1:
imm <<= 12; imm <<= 12;
break;
default:
unallocated_encoding(s);
return;
} }
tcg_result = tcg_temp_new_i64(tcg_ctx); tcg_result = tcg_temp_new_i64(tcg_ctx);
@ -4374,7 +4367,7 @@ static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
case 0x20: case 0x21: /* PC-rel. addressing */ case 0x20: case 0x21: /* PC-rel. addressing */
disas_pc_rel_adr(s, insn); disas_pc_rel_adr(s, insn);
break; break;
case 0x22: case 0x23: /* Add/subtract (immediate) */ case 0x22: /* Add/subtract (immediate) */
disas_add_sub_imm(s, insn); disas_add_sub_imm(s, insn);
break; break;
case 0x24: /* Logical (immediate) */ case 0x24: /* Logical (immediate) */