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target-mips: fix {RD, WR}PGPR in microMIPS

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rt, rs were swapped

Backports commit 1bf5902de03732d4067c4e90171a1741d6542c45 from qemu
This commit is contained in:
Yongbok Kim 2018-02-13 20:47:20 -05:00 committed by Lioncash
parent 80341ab1d8
commit af0e6e9be3
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target-mips/translate.c
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@ -13091,12 +13091,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
case RDPGPR:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
gen_load_srsgpr(ctx, rt, rs);
gen_load_srsgpr(ctx, rs, rt);
break;
case WRPGPR:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
gen_store_srsgpr(ctx, rt, rs);
gen_store_srsgpr(ctx, rs, rt);
break;
default:
goto pool32axf_invalid;