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riscv: spike: Remove target macro conditionals

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Backports dc4d4aaee31cd3ac4020d3b15729f0a104ce8862
This commit is contained in:
Alistair Francis 2021-03-08 15:20:39 -05:00 committed by Lioncash
parent 19c937f2cc
commit b23e786779
1 changed files with 0 additions and 8 deletions
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8
qemu/include/hw/riscv/spike.h
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@ -1,14 +1,6 @@
#ifndef HW_RISCV_SPIKE_H #ifndef HW_RISCV_SPIKE_H
#define HW_RISCV_SPIKE_H #define HW_RISCV_SPIKE_H
#if defined(TARGET_RISCV32)
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
#elif defined(TARGET_RISCV64)
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
#endif
void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc); void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc);
#endif /* HW_RISCV_SPIKE_H */ #endif /* HW_RISCV_SPIKE_H */