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target/mips: Add missing 'break' for a case of MTHC0 handling

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This was found by GCC 8.3 static analysis.

Fixes: 5fb2dcd1792

Backports commit ab8c34105a0ddd0c05159fb76919a18de8df4e8f from qemu
This commit is contained in:
Aleksandar Markovic 2019-08-08 19:36:30 -04:00 committed by Lioncash
parent cdb9422f3a
commit b2aa75be33
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qemu/target/mips/translate.c
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@ -6827,6 +6827,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
break;
case CP0_REGISTER_17:
switch (sel) {
case 0: