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target/mips: Add missing 'break' for a case of MTHC0 handling
This was found by GCC 8.3 static analysis. Fixes: 5fb2dcd1792 Backports commit ab8c34105a0ddd0c05159fb76919a18de8df4e8f from qemu
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@ -6827,6 +6827,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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default:
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default:
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goto cp0_unimplemented;
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goto cp0_unimplemented;
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}
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}
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break;
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case CP0_REGISTER_17:
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case CP0_REGISTER_17:
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switch (sel) {
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switch (sel) {
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case 0:
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case 0:
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