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target/mips: Enable CP0_EBase.WG on MIPS64 CPUs

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Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic
CPUs. This allows 64-bit guests to run KVM itself, which uses
CP0_EBase.WG to point CP0_EBase at XKPhys.

Backports commit bad63a8008a0aaefcd00542c89bee01623d7c9de from qemu
This commit is contained in:
James Hogan 2018-03-04 01:09:41 -05:00 committed by Lioncash
parent 16d97568e2
commit b35fb57c84
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target/mips/translate_init.c
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@ -871,7 +871,7 @@ static const mips_def_t mips_defs[] =
42,
36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
0,
(1 << CP0EBase_WG),
CPU_MIPS64R2 | ASE_MIPS3D,
MMU_TYPE_R4000,
},
@ -916,7 +916,7 @@ static const mips_def_t mips_defs[] =
(1 << CP0PG_ELPA),
(1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
(1U << CP0PG_RIE),
0,
(1 << CP0EBase_WG),
CPU_MIPS64R6 | ASE_MSA,
MMU_TYPE_R4000,
},