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target/mips: Enable CP0_EBase.WG on MIPS64 CPUs
Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic CPUs. This allows 64-bit guests to run KVM itself, which uses CP0_EBase.WG to point CP0_EBase at XKPhys. Backports commit bad63a8008a0aaefcd00542c89bee01623d7c9de from qemu
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@ -871,7 +871,7 @@ static const mips_def_t mips_defs[] =
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42,
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36,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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0,
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(1 << CP0EBase_WG),
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CPU_MIPS64R2 | ASE_MIPS3D,
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MMU_TYPE_R4000,
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},
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@ -916,7 +916,7 @@ static const mips_def_t mips_defs[] =
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(1 << CP0PG_ELPA),
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(1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
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(1U << CP0PG_RIE),
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0,
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(1 << CP0EBase_WG),
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CPU_MIPS64R6 | ASE_MSA,
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MMU_TYPE_R4000,
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},
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