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target/mips: MXU: Add missing opcodes/decoding for LX* instructions

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Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU,
and LXHU instructions. They were for some reason forgotten in
previous commits. The MXU opcode list and decoding engine should
be now complete.

Backports commit c233bf07af7cf2358b69c38150dbd2e3e4a399b6 from qemu
This commit is contained in:
Aleksandar Markovic 2019-01-05 07:33:57 -05:00 committed by Lioncash
parent 1c6732b053
commit b5e1ea2e08
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 15 additions and 6 deletions
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21
qemu/target/mips/translate.c
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@ -1657,12 +1657,21 @@ enum {
* │ 20..18
* ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW
* │ ├─ 001 ─ OPC_MXU_S32ALN
* ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI
* ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_S32NOR
* ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_S32AND
* ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR
* ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR
* ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI
* │ ├─ 010 ─ OPC_MXU_S32ALNI
* │ ├─ 011 ─ OPC_MXU_S32NOR
* │ ├─ 100 ─ OPC_MXU_S32AND
* │ ├─ 101 ─ OPC_MXU_S32OR
* │ ├─ 110 ─ OPC_MXU_S32XOR
* │ └─ 111 ─ OPC_MXU_S32LUI
* │
* │ 7..5
* ├─ 101000 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_LXB
* │ ├─ 001 ─ OPC_MXU_LXH
* ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_LXW
* ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_LXBU
* ├─ 101011 ─ OPC_MXU_S16STD └─ 101 ─ OPC_MXU_LXHU
* ├─ 101100 ─ OPC_MXU_S16LDI
* ├─ 101101 ─ OPC_MXU_S16SDI
* ├─ 101110 ─ OPC_MXU_S32M2I
* ├─ 101111 ─ OPC_MXU_S32I2M
* ├─ 110000 ─ OPC_MXU_D32SLL