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mips: Use DisasContext for parameters in place of TCGContext where applicable

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This is more future-friendly with qemu's main repo, as it's more
generic.
This commit is contained in:
Lioncash 2018-10-06 04:35:07 -04:00
parent 47b45f1bc2
commit b62e892b20
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 278 additions and 267 deletions
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9
qemu/target/arm/translate-a64.c
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@ -1330,9 +1330,10 @@ bool sve_access_check(DisasContext *s)
* optional shift. You will likely want to pass a temporary for the * optional shift. You will likely want to pass a temporary for the
* destination register. See DecodeRegExtend() in the ARM ARM. * destination register. See DecodeRegExtend() in the ARM ARM.
*/ */
static void ext_and_shift_reg(TCGContext *tcg_ctx, TCGv_i64 tcg_out, TCGv_i64 tcg_in, static void ext_and_shift_reg(DisasContext *s, TCGv_i64 tcg_out, TCGv_i64 tcg_in,
int option, unsigned int shift) int option, unsigned int shift)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int extsize = extract32(option, 0, 2); int extsize = extract32(option, 0, 2);
bool is_signed = extract32(option, 2, 1); bool is_signed = extract32(option, 2, 1);
@ -2834,7 +2835,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
tcg_addr = read_cpu_reg_sp(s, rn, 1); tcg_addr = read_cpu_reg_sp(s, rn, 1);
tcg_rm = read_cpu_reg(s, rm, 1); tcg_rm = read_cpu_reg(s, rm, 1);
ext_and_shift_reg(tcg_ctx, tcg_rm, tcg_rm, opt, shift ? size : 0); ext_and_shift_reg(s, tcg_rm, tcg_rm, opt, shift ? size : 0);
tcg_gen_add_i64(tcg_ctx, tcg_addr, tcg_addr, tcg_rm); tcg_gen_add_i64(tcg_ctx, tcg_addr, tcg_addr, tcg_rm);
@ -4053,7 +4054,7 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
tcg_rn = read_cpu_reg_sp(s, rn, sf); tcg_rn = read_cpu_reg_sp(s, rn, sf);
tcg_rm = read_cpu_reg(s, rm, sf); tcg_rm = read_cpu_reg(s, rm, sf);
ext_and_shift_reg(tcg_ctx, tcg_rm, tcg_rm, option, imm3); ext_and_shift_reg(s, tcg_rm, tcg_rm, option, imm3);
tcg_result = tcg_temp_new_i64(tcg_ctx); tcg_result = tcg_temp_new_i64(tcg_ctx);
@ -9964,7 +9965,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
for (i = 0; i < elements; i++) { for (i = 0; i < elements; i++) {
tcg_gen_shri_i64(tcg_ctx, tcg_rd, tcg_rn, i * esize); tcg_gen_shri_i64(tcg_ctx, tcg_rd, tcg_rn, i * esize);
ext_and_shift_reg(tcg_ctx, tcg_rd, tcg_rd, size | (!is_u << 2), 0); ext_and_shift_reg(s, tcg_rd, tcg_rd, size | (!is_u << 2), 0);
tcg_gen_shli_i64(tcg_ctx, tcg_rd, tcg_rd, shift); tcg_gen_shli_i64(tcg_ctx, tcg_rd, tcg_rd, shift);
write_vec_element(s, tcg_rd, rd, i, size + 1); write_vec_element(s, tcg_rd, rd, i, size + 1);
} }

532
qemu/target/mips/translate.c
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