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target/arm: Swap PMU values before/after migrations

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Because of the PMU's design, many register accesses have side effects
which are inter-related, meaning that the normal method of saving CP
registers can result in inconsistent state. These side-effects are
largely handled in pmu_op_start/finish functions which can be called
before and after the state is saved/restored. By doing this and adding
raw read/write functions for the affected registers, we avoid
migration-related inconsistencies.

Backports relevant parts of commit
980ebe87053792a5bdefaa87777c40914fd4f673 from qemu
This commit is contained in:
Aaron Lindsay 2019-01-22 17:01:32 -05:00 committed by Lioncash
parent 001283c45b
commit b6b0c18ce5
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 3 deletions
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6
qemu/target/arm/helper.c
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@ -1299,12 +1299,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
ARM_CP_ALIAS | ARM_CP_IO, PL0_RW, 0, NULL, 0, 0, {0, 0},
pmreg_access_ccntr, pmccntr_read, pmccntr_write32, },
{ "PMCCNTR_EL0", 0,9,13, 3,3,0, ARM_CP_STATE_AA64,
ARM_CP_IO, PL0_RW, 0, NULL, 0, 0, {0, 0},
pmreg_access_ccntr, pmccntr_read, pmccntr_write, },
ARM_CP_IO, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c15_ccnt), {0, 0},
pmreg_access_ccntr, pmccntr_read, pmccntr_write, raw_read, raw_write },
#endif
{ "PMCCFILTR_EL0", 0,14,15, 3,3,7, ARM_CP_STATE_AA64,
ARM_CP_IO, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmccfiltr_el0), {0, 0},
pmreg_access, NULL, pmccfiltr_write, },
pmreg_access, NULL, pmccfiltr_write, NULL, raw_write },
{ "PMXEVTYPER", 15,9,13, 0,0,1, 0, ARM_CP_NO_RAW,
PL0_RW, 0, NULL, 0, 0, {0, 0},
pmreg_access, pmxevtyper_read, pmxevtyper_write },