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target/arm: Remove CPSR_RESERVED

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The only remaining use was in op_helper.c. Use PSTATE_SS
directly, and move the commentary so that it is more obvious
what is going on.

Backports commit 70dae0d069c45250bbefd9424089383a8ac239de from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:24:19 -04:00 committed by Lioncash
parent 2d3239d0a1
commit b6b69d7ac5
2 changed files with 8 additions and 7 deletions
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6
qemu/target/arm/cpu.h
View file

@ -1071,12 +1071,6 @@ void pmu_init(ARMCPU *cpu);
#define CPSR_IT_2_7 (0xfc00U) #define CPSR_IT_2_7 (0xfc00U)
#define CPSR_GE (0xfU << 16) #define CPSR_GE (0xfU << 16)
#define CPSR_IL (1U << 20) #define CPSR_IL (1U << 20)
/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
* an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
* env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
* where it is live state but not accessible to the AArch32 code.
*/
#define CPSR_RESERVED (0x7U << 21)
#define CPSR_J (1U << 24) #define CPSR_J (1U << 24)
#define CPSR_IT_0_1 (3U << 25) #define CPSR_IT_0_1 (3U << 25)
#define CPSR_Q (1U << 27) #define CPSR_Q (1U << 27)

9
qemu/target/arm/op_helper.c
View file

@ -394,7 +394,14 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
uint32_t HELPER(cpsr_read)(CPUARMState *env) uint32_t HELPER(cpsr_read)(CPUARMState *env)
{ {
return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED); /*
* We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
* This is convenient for populating SPSR_ELx, but must be
* hidden from aarch32 mode, where it is not visible.
*
* TODO: ARMv8.4-DIT -- need to move SS somewhere else.
*/
return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
} }
void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)