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target-arm: make MAIR0/1 banked

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Added CP register info entries for the ARMv7 MAIR0/1 secure banks.

Backports commit be693c87e440e671ed913784554384349ce8331d from qemu
This commit is contained in:
Greg Bellows 2018-02-12 10:02:48 -05:00 committed by Lioncash
parent 4bf69e19c6
commit b711147cc3
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 29 additions and 4 deletions
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21
qemu/target-arm/cpu.h
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@ -298,7 +298,26 @@ typedef struct CPUARMState {
uint32_t c9_pmxevtyper; /* perf monitor event type */
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
union { /* Memory attribute redirection */
struct {
#ifdef HOST_WORDS_BIGENDIAN
uint64_t _unused_mair_0;
uint32_t mair1_ns;
uint32_t mair0_ns;
uint64_t _unused_mair_1;
uint32_t mair1_s;
uint32_t mair0_s;
#else
uint64_t _unused_mair_0;
uint32_t mair0_ns;
uint32_t mair1_ns;
uint64_t _unused_mair_1;
uint32_t mair0_s;
uint32_t mair1_s;
#endif
};
uint64_t mair_el[4];
};
union { /* vector base address register */
struct {
uint64_t _unused_vbar;

12
qemu/target-arm/helper.c
View file

@ -808,17 +808,23 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
* and so don't need to care about memory attributes.
*/
{ "MAIR_EL1", 0,10,2, 3,0,0, ARM_CP_STATE_AA64,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el1), },
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[1]), },
/* For non-long-descriptor page tables these are PRRR and NMRR;
* regardless they still act as reads-as-written for QEMU.
* The override is necessary because of the overly-broad TLB_LOCKDOWN
* definition.
*/
/* MAIR0/1 are defined separately from their 64-bit counterpart which
* allows them to assign the correct fieldoffset based on the endianness
* handled in the field definitions.
*/
{ "MAIR0", 15,10,2, 0,0,0, ARM_CP_STATE_AA32,
ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.mair_el1), {0, 0},
ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.mair0_s), offsetof(CPUARMState, cp15.mair0_ns) },
NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
{ "MAIR1", 15,10,2, 0,0,1, ARM_CP_STATE_AA32,
ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.mair_el1), {0, 0},
ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.mair1_s), offsetof(CPUARMState, cp15.mair1_ns) },
NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
{ "ISR_EL1", 0,12,1, 3,0,0, ARM_CP_STATE_BOTH,
ARM_CP_NO_MIGRATE, PL1_R, 0, NULL, 0, 0, {0, 0},