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target-arm: Pass timeridx as argument to various timer functions

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Prepare for adding the Hypervisor timer, no functional change.

Backports commit 0e3eca4c26d6aa4f082db8e63fd81a16df061f3c from qemu
This commit is contained in:
Lioncash 2018-02-14 20:07:33 -05:00
parent 4cbd161ea8
commit ba27ba76a4
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 75 additions and 19 deletions
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94
qemu/target-arm/helper.c
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@ -1108,7 +1108,8 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
}
}
static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx)
{
}
@ -1123,17 +1124,16 @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
}
static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx,
uint64_t value)
{
int timeridx = ri->opc1 & 1;
env->cp15.c14_timer[timeridx].cval = value;
//gt_recalc_timer(arm_env_get_cpu(env), timeridx);
}
static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx)
{
int timeridx = ri->crm & 1;
uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
@ -1141,9 +1141,9 @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
}
static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx,
uint64_t value)
{
int timeridx = ri->crm & 1;
uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
@ -1152,10 +1152,10 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int timeridx = ri->crm & 1;
uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
@ -1171,6 +1171,62 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
}
static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
gt_timer_reset(env, ri, GTIMER_PHYS);
}
static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_cval_write(env, ri, GTIMER_PHYS, value);
}
static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return gt_tval_read(env, ri, GTIMER_PHYS);
}
static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_tval_write(env, ri, GTIMER_PHYS, value);
}
static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_ctl_write(env, ri, GTIMER_PHYS, value);
}
static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
gt_timer_reset(env, ri, GTIMER_VIRT);
}
static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_cval_write(env, ri, GTIMER_VIRT, value);
}
static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return gt_tval_read(env, ri, GTIMER_VIRT);
}
static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_tval_write(env, ri, GTIMER_VIRT, value);
}
static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_ctl_write(env, ri, GTIMER_VIRT, value);
}
static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@ -1211,29 +1267,29 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
/* per-timer control */
{ "CNTP_CTL", 15,14,2, 0,0,1, 0,
ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), {0, 0},
gt_ptimer_access, NULL, gt_ctl_write, NULL, raw_write, NULL },
gt_ptimer_access, NULL, gt_phys_ctl_write, NULL, raw_write, NULL },
{ "CNTP_CTL_EL0", 0,14,2, 3,3,1, ARM_CP_STATE_AA64,
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), {0, 0},
gt_ptimer_access, NULL,gt_ctl_write, NULL,raw_write, },
gt_ptimer_access, NULL,gt_phys_ctl_write, NULL,raw_write, },
{ "CNTV_CTL", 15,14,3, 0,0,1, 0,
ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), {0, 0},
gt_vtimer_access, NULL, gt_ctl_write, NULL, raw_write, NULL },
gt_vtimer_access, NULL, gt_virt_ctl_write, NULL, raw_write, NULL },
{ "CNTV_CTL_EL0", 0,14,3, 3,3,1, ARM_CP_STATE_AA64,
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), {0, 0},
gt_vtimer_access, NULL,gt_ctl_write, NULL,raw_write, },
gt_vtimer_access, NULL,gt_virt_ctl_write, NULL,raw_write, },
/* TimerValue views: a 32 bit downcounting view of the underlying state */
{ "CNTP_TVAL", 15,14,2, 0,0,0, 0,
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
gt_ptimer_access, gt_tval_read, gt_tval_write, },
gt_ptimer_access, gt_phys_tval_read, gt_phys_tval_write, },
{ "CNTP_TVAL_EL0", 0,14,2, 3,3,0, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
gt_ptimer_access, gt_tval_read, gt_tval_write, NULL, NULL, gt_timer_reset },
gt_ptimer_access, gt_phys_tval_read, gt_phys_tval_write, NULL, NULL, gt_phys_timer_reset },
{ "CNTV_TVAL", 15,14,3, 0,0,0, 0,
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
gt_vtimer_access, gt_tval_read, gt_tval_write, },
gt_vtimer_access, gt_virt_tval_read, gt_virt_tval_write, },
{ "CNTV_TVAL_EL0", 0,14,3, 3,3,0, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
gt_vtimer_access, gt_tval_read, gt_tval_write, NULL, NULL, gt_timer_reset },
gt_vtimer_access, gt_virt_tval_read, gt_virt_tval_write, NULL, NULL, gt_virt_timer_reset },
/* The counter itself */
{ "CNTPCT", 15,0,14, 0,0, 0, 0,
ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, PL0_R, 0, NULL, 0, 0, {0, 0},
@ -1250,16 +1306,16 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
/* Comparison value, indicating when the timer goes off */
{ "CNTP_CVAL", 15, 0,14, 0,2, 0, 0,
ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), {0, 0},
gt_ptimer_access, NULL, gt_cval_write, NULL, raw_write, NULL },
gt_ptimer_access, NULL, gt_phys_cval_write, NULL, raw_write, NULL },
{ "CNTP_CVAL_EL0", 0,14,2, 3,3,2, ARM_CP_STATE_AA64,
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), {0, 0},
gt_ptimer_access, NULL, gt_cval_write, NULL, raw_write, },
gt_ptimer_access, NULL, gt_phys_cval_write, NULL, raw_write, },
{ "CNTV_CVAL", 15, 0,14, 0,3,0, 0,
ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), {0, 0},
gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, NULL },
gt_vtimer_access, NULL, gt_virt_cval_write, NULL, raw_write, NULL },
{ "CNTV_CVAL_EL0", 0,14,3, 3,3,2, ARM_CP_STATE_AA64,
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), {0, 0},
gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, },
gt_vtimer_access, NULL, gt_virt_cval_write, NULL, raw_write, },
REGINFO_SENTINEL
};