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target/arm: Suppress TB end for FPCR/FPSR

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Nothing in either register affects the TB.

Backports commit b916c9c35ce8158bf7f9ed5514eb279e52875de2 from qemu
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Richard Henderson 2018-03-08 09:08:53 -05:00 committed by Lioncash
parent d5c4d3e3c3
commit c095dc9e83
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target/arm/helper.c
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@ -3064,10 +3064,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ "DAIF", 0,4,2, 3,3,1, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, daif), {0, 0},
aa64_daif_access, NULL, aa64_daif_write, NULL,NULL, arm_cp_reset_ignore },
{ "FPCR", 0,4,4, 3,3,0, ARM_CP_STATE_AA64, ARM_CP_FPU,
{ "FPCR", 0,4,4, 3,3,0, ARM_CP_STATE_AA64, ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
PL0_RW, 0, NULL, 0, 0, {0, 0},
NULL, aa64_fpcr_read, aa64_fpcr_write },
{ "FPSR", 0,4,4, 3,3,1, ARM_CP_STATE_AA64, ARM_CP_FPU,
{ "FPSR", 0,4,4, 3,3,1, ARM_CP_STATE_AA64, ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
PL0_RW, 0, NULL, 0, 0, {0, 0},
NULL, aa64_fpsr_read, aa64_fpsr_write },
{ "DCZID_EL0", 0,0,0, 3,3,7, ARM_CP_STATE_AA64,