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target/arm: Implement AArch32 Hyp FARs

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The AArch32 virtualization extensions support these fault address
registers:
* HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S)
* HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S)

Implement the accessors for these. This fixes in passing a bug
where we weren't implementing the "RES0 from EL3 if EL2 not
implemented" behaviour for AArch64 FAR_EL2.

Backports commit cba517c31e7df8932c4473c477a0f01d8a0adc48 from qemu
This commit is contained in:
Peter Maydell 2018-08-22 12:45:21 -04:00 committed by Lioncash
parent 763a71a962
commit c21d2062e4
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 1 deletions
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8
qemu/target/arm/helper.c
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@ -3406,6 +3406,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
access_el3_aa32ns_aa64any },
{ "HSTR_EL2", 0,1,1, 3,4,3, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "HIFAR", 15,6,0, 0,4,2, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
REGINFO_SENTINEL
};
@ -3449,8 +3453,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) },
{ "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
{ "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_AA64,
{ "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_BOTH,
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },
{ "HIFAR", 15,6,0, 0,4,2, ARM_CP_STATE_AA32,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.far_el[2]) },
{ "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
{ "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_BOTH,