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target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH
Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by Coverity (CID 1395627). Backports commit d5ebcbaf09e8c14e62b2966446195be5eeabcbab from qemu
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@ -20109,8 +20109,8 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
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case 0:
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case 0:
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/* SHRA_PH */
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/* SHRA_PH */
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gen_helper_shra_ph(tcg_ctx, v1_t, t0, v1_t);
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gen_helper_shra_ph(tcg_ctx, v1_t, t0, v1_t);
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break;
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gen_store_gpr(ctx, v1_t, rt);
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gen_store_gpr(ctx, v1_t, rt);
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break;
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case 1:
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case 1:
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/* SHRA_R_PH */
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/* SHRA_R_PH */
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gen_helper_shra_r_ph(tcg_ctx, v1_t, t0, v1_t);
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gen_helper_shra_r_ph(tcg_ctx, v1_t, t0, v1_t);
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