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target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half

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We were using the wrong flush-to-zero bit for the non-half input.

Fixes: 46d33d1e3c9

Backports commit e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4 from qemu
This commit is contained in:
Richard Henderson 2018-08-17 14:05:09 -04:00 committed by Lioncash
parent 118495f4b1
commit c387d51c1d
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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qemu/target/arm/translate-sve.c
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@ -4255,7 +4255,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh);
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
}
static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
@ -4265,7 +4265,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh);
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
}
static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)