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https://github.com/yuzu-emu/unicorn.git
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target-mips: add Config5.FRE support allowing Status.FR=0 emulation
This relatively small architectural feature adds the following: FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available. Config5.FRE: When enabled all single-precision FP arithmetic instructions, LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions exception. Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions. Enable the feature in MIPS64R6-generic CPU. Backports commit 7c979afd11b09a16634699dd6344e3ba10c9677e from qemu
This commit is contained in:
Leon Alrae
Lioncash
parent
428ffed744
commit
c54458b638
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@ -101,6 +101,7 @@ struct CPUMIPSFPUContext {
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float_status fp_status;
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/* fpu implementation/revision register (fir) */
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uint32_t fcr0;
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#define FCR0_FREP 29
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#define FCR0_UFRP 28
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#define FCR0_F64 22
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#define FCR0_L 21
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@ -463,6 +464,8 @@ struct CPUMIPSState {
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#define CP0C5_CV 29
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#define CP0C5_EVA 28
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#define CP0C5_MSAEn 27
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#define CP0C5_UFE 9
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#define CP0C5_FRE 8
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#define CP0C5_SBRI 6
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#define CP0C5_UFR 2
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#define CP0C5_NFExists 0
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@ -515,7 +518,7 @@ struct CPUMIPSState {
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#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
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uint32_t hflags; /* CPU State */
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/* TMASK defines different execution modes */
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#define MIPS_HFLAG_TMASK 0x15807FF
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#define MIPS_HFLAG_TMASK 0x35807FF
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#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
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/* The KSU flags must be the lowest bits in hflags. The flag order
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must be the same as defined for CP0 Status. This allows to use
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@ -561,7 +564,8 @@ struct CPUMIPSState {
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#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
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#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
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#define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
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#define MIPS_HFLAG_MSA 0x1000000
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#define MIPS_HFLAG_MSA 0x1000000 /* FRE enabled */
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#define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
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target_ulong btarget; /* Jump / branch target */
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target_ulong bcond; /* Branch condition (if needed) */
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@ -847,7 +851,7 @@ static inline void compute_hflags(CPUMIPSState *env)
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env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
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MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
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MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
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MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA);
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MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE);
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if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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@ -928,6 +932,11 @@ static inline void compute_hflags(CPUMIPSState *env)
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env->hflags |= MIPS_HFLAG_MSA;
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}
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}
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if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
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if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
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env->hflags |= MIPS_HFLAG_FRE;
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}
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}
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}
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#ifndef CONFIG_USER_ONLY
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@ -2306,6 +2306,16 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
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}
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}
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break;
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case 5:
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/* FRE Support - read Config5.FRE bit */
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if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
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if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
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arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
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} else {
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helper_raise_exception(env, EXCP_RI);
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}
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}
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break;
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case 25:
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arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
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break;
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@ -2350,6 +2360,30 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
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helper_raise_exception(env, EXCP_RI);
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}
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break;
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case 5:
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/* FRE Support - clear Config5.FRE bit */
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if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
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return;
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}
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if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
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env->CP0_Config5 &= ~(1 << CP0C5_FRE);
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compute_hflags(env);
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} else {
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helper_raise_exception(env, EXCP_RI);
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}
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break;
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case 6:
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/* FRE Support - set Config5.FRE bit */
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if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
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return;
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}
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if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
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env->CP0_Config5 |= (1 << CP0C5_FRE);
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compute_hflags(env);
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} else {
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helper_raise_exception(env, EXCP_RI);
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}
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break;
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case 25:
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if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
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return;
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@ -1548,20 +1548,22 @@ static inline void gen_store_srsgpr (DisasContext *s, int from, int to)
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}
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/* Tests */
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static inline void gen_save_pc(target_ulong pc)
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static inline void gen_save_pc(DisasContext *ctx, target_ulong pc)
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{
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tcg_gen_movi_tl(cpu_PC, pc);
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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tcg_gen_movi_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_PC, pc);
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}
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static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
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if (do_save_pc && ctx->pc != ctx->saved_pc) {
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gen_save_pc(ctx->pc);
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gen_save_pc(ctx, ctx->pc);
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ctx->saved_pc = ctx->pc;
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}
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if (ctx->hflags != ctx->saved_hflags) {
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tcg_gen_movi_i32(hflags, ctx->hflags);
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->hflags, ctx->hflags);
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ctx->saved_hflags = ctx->hflags;
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switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
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case MIPS_HFLAG_BR:
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@ -1569,7 +1571,7 @@ static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
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case MIPS_HFLAG_BC:
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case MIPS_HFLAG_BL:
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case MIPS_HFLAG_B:
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tcg_gen_movi_tl(btarget, ctx->btarget);
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tcg_gen_movi_tl(tcg_ctx, *(TCGv *)tcg_ctx->btarget, ctx->btarget);
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break;
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}
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}
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@ -1591,31 +1593,41 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
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static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
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{
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TCGv_i32 texcp = tcg_const_i32(excp);
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TCGv_i32 terr = tcg_const_i32(err);
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv_i32 texcp = tcg_const_i32(tcg_ctx, excp);
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TCGv_i32 terr = tcg_const_i32(tcg_ctx, err);
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save_cpu_state(ctx, 1);
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gen_helper_raise_exception_err(cpu_env, texcp, terr);
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tcg_temp_free_i32(terr);
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tcg_temp_free_i32(texcp);
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gen_helper_raise_exception_err(tcg_ctx, tcg_ctx->cpu_env, texcp, terr);
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tcg_temp_free_i32(tcg_ctx, terr);
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tcg_temp_free_i32(tcg_ctx, texcp);
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}
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static inline void generate_exception(DisasContext *ctx, int excp)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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save_cpu_state(ctx, 1);
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gen_helper_0e0i(raise_exception, excp);
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gen_helper_0e0i(tcg_ctx, raise_exception, excp);
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}
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/* Floating point register moves. */
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static void gen_load_fpr32(DisasContext *s, TCGv_i32 t, int reg)
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static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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if (ctx->hflags & MIPS_HFLAG_FRE) {
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generate_exception(ctx, EXCP_RI);
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}
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tcg_gen_extrl_i64_i32(tcg_ctx, t, tcg_ctx->fpu_f64[reg]);
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}
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static void gen_store_fpr32(DisasContext *s, TCGv_i32 t, int reg)
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static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i64 t64 = tcg_temp_new_i64(tcg_ctx);
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv_i64 t64;
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if (ctx->hflags & MIPS_HFLAG_FRE) {
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generate_exception(ctx, EXCP_RI);
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}
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t64 = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_extu_i32_i64(tcg_ctx, t64, t);
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tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->fpu_f64[reg], tcg_ctx->fpu_f64[reg], t64, 0, 32);
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tcg_temp_free_i64(tcg_ctx, t64);
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@ -8523,7 +8535,8 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
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gen_set_label(tcg_ctx, l1);
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}
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static inline void gen_movcf_s (DisasContext *ctx, int fs, int fd, int cc, int tf)
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static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
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int tf)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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int cond;
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@ -739,7 +739,7 @@ static const mips_def_t mips_defs[] =
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(3 << CP0C4_IE) | (1 << CP0C4_M),
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0,
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0,
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(1 << CP0C5_SBRI),
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(1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
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0,
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0,
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0,
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@ -749,9 +749,9 @@ static const mips_def_t mips_defs[] =
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0x30D8FFFF,
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0,
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0,
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
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(0x0 << FCR0_REV),
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(1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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0,
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42,
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/* The architectural limit is 59, but we have hardcoded 36 bit
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