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target-i386: allow any alignment for SMBASE

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Processors up to the Pentium (says Bochs---I do not have old enough
manuals) require a 32KiB alignment for the SMBASE, but newer processors
do not need that, and Tiano Core will use non-aligned SMBASE values.

Backports commit dd75d4fcb4a82c34d4f466e7fc166162b71ff740 from qemu
This commit is contained in:
Paolo Bonzini 2018-02-16 16:00:10 -05:00 committed by Lioncash
parent 924d4599cc
commit c5c44f3a8a
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target-i386/smm_helper.c
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@ -256,7 +256,7 @@ void helper_rsm(CPUX86State *env)
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) { if (val & 0x20000) {
env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00) & ~0x7fff; env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
} }
#else #else
cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
@ -309,7 +309,7 @@ void helper_rsm(CPUX86State *env)
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) { if (val & 0x20000) {
env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8) & ~0x7fff; env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
} }
#endif #endif
if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) { if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {