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tcg: enable MTTCG by default for ARM on x86 hosts
This enables the multi-threaded system emulation by default for ARMv7 and ARMv8 guests using the x86_64 TCG backend. This is because on the guest side: - The ARM translate.c/translate-64.c have been converted to - use MTTCG safe atomic primitives - emit the appropriate barrier ops - The ARM machine has been updated to - hold the BQL when modifying shared cross-vCPU state - defer powerctl changes to async safe work All the host backends support the barrier and atomic primitives but need to provide same-or-better support for normal load/store operations. Backports commit ca759f9e387db87e1719911f019bc60c74be9ed8 from qemu
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caba238b5a
6
qemu/configure
vendored
6
qemu/configure
vendored
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@ -1320,6 +1320,7 @@ mkdir -p $target_dir
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echo "# Automatically generated by configure - do not modify" > $config_target_mak
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bflt="no"
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mttcg="no"
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TARGET_ARCH="$target_name"
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TARGET_BASE_ARCH=""
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@ -1334,12 +1335,14 @@ case "$target_name" in
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;;
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arm|armeb)
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TARGET_ARCH=arm
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mttcg="yes"
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bflt="yes"
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;;
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aarch64|aarch64eb)
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TARGET_BASE_ARCH=arm
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TARGET_ARCH=aarch64
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bflt="yes"
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mttcg="yes"
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;;
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cris)
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;;
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@ -1437,6 +1440,9 @@ if test "$target_bigendian" = "yes" ; then
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fi
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if test "$target_softmmu" = "yes" ; then
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echo "CONFIG_SOFTMMU=y" >> $config_target_mak
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if test "$mttcg" = "yes" ; then
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echo "TARGET_SUPPORTS_MTTCG=y" >> $config_target_mak
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fi
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fi
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# generate QEMU_CFLAGS/LDFLAGS for targets
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@ -33,6 +33,9 @@
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#define TARGET_IS_BIENDIAN 1
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/* ARM processors have a weak memory model */
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#define TCG_GUEST_DEFAULT_MO (0)
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#define CPUArchState struct CPUARMState
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#include "qemu-common.h"
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@ -165,4 +165,15 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
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{
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}
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/* This defines the natural memory order supported by this
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* architecture before guarantees made by various barrier
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* instructions.
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*
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* The x86 has a pretty strong memory ordering which only really
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* allows for some stores to be re-ordered after loads.
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*/
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#include "tcg-mo.h"
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#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
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#endif
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